Texas Instruments RM46 Hercules Safety MCU controlCARD TMDXRM46CNCD TMDXRM46CNCD Datenbogen
Produktcode
TMDXRM46CNCD
SDA
SCL
t
w(SDAH)
t
w(SCLL)
t
w(SCLH)
t
w(SP)
t
h(SCLL-SDAL)
t
h(SDA-SCLL)
t
h(SCLL-SDAL)
t
su(SCLH-SDAL)
t
f(SCL)
t
c(SCL)
t
r(SCL)
t
su(SCLH-SDAH)
Stop
Start
Repeated Start
Stop
t
su(SDA-SCLH)
SPNS184A – SEPTEMBER 2012 – REVISED SEPTEMBER 2013
5.10.2 I2C I/O Timing Specifications
Table 5-27. I2C Signals (SDA and SCL) Switching Characteristics
(1)
Parameter
Standard Mode
Fast Mode
Unit
MIN
MAX
MIN
MAX
t
c(I2CCLK)
Cycle time, Internal Module clock for I2C,
75.2
149
75.2
149
ns
prescaled from VCLK
f
(SCL)
SCL Clock frequency
0
100
0
400
kHz
t
c(SCL)
Cycle time, SCL
10
2.5
µs
t
su(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
4.7
0.6
µs
repeated START condition)
t
h(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated
4
0.6
µs
START condition)
t
w(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
t
w(SCLH)
Pulse duration, SCL high
4
0.6
µs
t
su(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
ns
t
h(SDA-SCLL)
Hold time, SDA valid after SCL low (for I2C bus
0
3.45
(2)
0
0.9
µs
devices)
t
w(SDAH)
Pulse duration, SDA high between STOP and
4.7
1.3
µs
START conditions
t
su(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP
4.0
0.6
µs
condition)
t
w(SP)
Pulse duration, spike (must be suppressed)
0
50
ns
C
b
(3)
Capacitive load for each bus line
400
400
pF
(1)
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
down.
(2)
The maximum t
h(SDA-SCLL)
for I2C bus devices has only to be met if the device does not stretch the low period (t
w(SCLL)
) of the SCL
signal.
(3)
C
b
= The total capacitance of one bus line in pF.
Figure 5-13. I2C Timings
150
Peripheral Information and Electrical Specifications
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