Benutzerhandbuch für Texas Instruments RM46 Hercules Safety MCU controlCARD TMDXRM46CNCD

Inhaltsverzeichnis

• 1 RM46Lx50 16- and 32-Bit RISC Flash Microcontroller

  1
  • 1.1 Features

    1
  • 1.2 Applications

    2
  • 1.3 Description

    3
  • 1.4 Functional Block Diagram

    5
• Table of Contents

  7
• Revision History

  8
• 2 Device Package and Terminal Functions

  9
  • 2.1 PGE QFP Package Pinout (144-Pin)

    9
  • 2.2 ZWT BGA Package Ball-Map (337 Ball Grid Array)

    10
  • 2.3 Terminal Functions

    11
    • 2.3.1 PGE Package

      11
      • 2.3.1.1 Multi-Buffered Analog-to-Digital Converters (MibADC)

        11
      • 2.3.1.2 Enhanced High-End Timer Modules (N2HET)

        13
      • 2.3.1.3 Enhanced Capture Modules (eCAP)

        14
      • 2.3.1.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

        15
      • 2.3.1.5 Enhanced Pulse-Width Modulator Modules (ePWM)

        16
      • 2.3.1.6 General-Purpose Input / Output (GPIO)

        17
      • 2.3.1.7 Controller Area Network Controllers (DCAN)

        17
      • 2.3.1.8 Local Interconnect Network Interface Module (LIN)

        17
      • 2.3.1.9 Standard Serial Communication Interface (SCI)

        18
      • 2.3.1.10 Inter-Integrated Circuit Interface Module (I2C)

        18
      • 2.3.1.11 Standard Serial Peripheral Interface (SPI)

        18
      • 2.3.1.12 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

        19
      • 2.3.1.13 Ethernet Controller

        20
      • 2.3.1.14 USB Host Port Controller Interface

        21
      • 2.3.1.15 System Module Interface

        22
      • 2.3.1.16 Clock Inputs and Outputs

        23
      • 2.3.1.17 Test and Debug Modules Interface

        23
      • 2.3.1.18 Flash Supply and Test Pads

        23
      • 2.3.1.19 Supply for Core Logic: 1.2V nominal

        24
      • 2.3.1.20 Supply for I/O Cells: 3.3V nominal

        24
      • 2.3.1.21 Ground Reference for All Supplies Except VCCAD

        25
    • 2.3.2 ZWT Package

      26
      • 2.3.2.1 Multi-Buffered Analog-to-Digital Converters (MibADC)

        26
      • 2.3.2.2 Enhanced High-End Timer Modules (N2HET)

        27
      • 2.3.2.3 Enhanced Capture Modules (eCAP)

        28
      • 2.3.2.4 Enhanced Quadrature Encoder Pulse Modules (eQEP)

        29
      • 2.3.2.5 Enhanced Pulse-Width Modulator Modules (ePWM)

        30
      • 2.3.2.6 General-Purpose Input / Output (GPIO)

        31
      • 2.3.2.7 Controller Area Network Controllers (DCAN)

        32
      • 2.3.2.8 Local Interconnect Network Interface Module (LIN)

        32
      • 2.3.2.9 Standard Serial Communication Interface (SCI)

        32
      • 2.3.2.10 Inter-Integrated Circuit Interface Module (I2C)

        33
      • 2.3.2.11 Standard Serial Peripheral Interface (SPI)

        33
      • 2.3.2.12 Multi-Buffered Serial Peripheral Interface Modules (MibSPI)

        34
      • 2.3.2.13 Ethernet Controller

        36
      • 2.3.2.14 USB Host Port Controller Interface

        38
      • 2.3.2.15 External Memory Interface (EMIF)

        40
      • 2.3.2.16 System Module Interface

        42
      • 2.3.2.17 Clock Inputs and Outputs

        42
      • 2.3.2.18 Test and Debug Modules Interface

        43
      • 2.3.2.19 Flash Supply and Test Pads

        43
      • 2.3.2.20 No Connects

        43
      • 2.3.2.21 Supply for Core Logic: 1.2V nominal

        46
      • 2.3.2.22 Supply for I/O Cells: 3.3V nominal

        47
      • 2.3.2.23 Ground Reference for All Supplies Except VCCAD

        48
• 3 Device Operating Conditions

  49
  • 3.1  Absolute Maximum Ratings Over Operating Free-Air Temperature Range,

    49
  • 3.2 Device Recommended Operating Conditions

    49
  • 3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains

    50
  • 3.4 Wait States Required

    50
  • 3.5 Power Consumption Over Recommended Operating Conditions

    51
  • 3.6 Input/Output Electrical Characteristics Over Recommended Operating Conditions

    52
  • 3.7 Output Buffer Drive Strengths

    53
  • 3.8 Input Timings

    54
  • 3.9 Output Timings

    54
  • 3.10 Low-EMI Output Buffers

    56
• 4 System Information and Electrical Specifications

  57
  • 4.1 Device Power Domains

    57
  • 4.2 Voltage Monitor Characteristics

    57
    • 4.2.1 Important Considerations

      57
    • 4.2.2 Voltage Monitor Operation

      57
    • 4.2.3 Supply Filtering

      58
  • 4.3 Power Sequencing and Power On Reset

    59
    • 4.3.1 Power-Up Sequence

      59
    • 4.3.2 Power-Down Sequence

      59
    • 4.3.3 Power-On Reset: nPORRST

      59
      • 4.3.3.1 nPORRST Electrical and Timing Requirements

        59
  • 4.4 Warm Reset (nRST)

    61
    • 4.4.1 Causes of Warm Reset

      61
    • 4.4.2 nRST Timing Requirements

      61
  • 4.5 ARM© Cortex-R4F™ CPU Information

    62
    • 4.5.1 Summary of ARM Cortex-R4F™ CPU Features

      62
    • 4.5.2 ARM Cortex-R4F™ CPU Features Enabled by Software

      62
    • 4.5.3 Dual Core Implementation

      62
    • 4.5.4 Duplicate clock tree after GCLK

      63
    • 4.5.5 ARM Cortex-R4F™ CPU Compare Module (CCM-R4) for Safety

      63
    • 4.5.6 CPU Self-Test

      63
      • 4.5.6.1 Application Sequence for CPU Self-Test

        64
      • 4.5.6.2 CPU Self-Test Clock Configuration

        64
      • 4.5.6.3 CPU Self-Test Coverage

        64
  • 4.6 Clocks

    65
    • 4.6.1 Clock Sources

      65
      • 4.6.1.1 Main Oscillator

        65
      • 4.6.1.2 Low Power Oscillator

        67
      • 4.6.1.3 Phase Locked Loop (PLL) Clock Modules

        68
      • 4.6.1.4 External Clock Inputs

        69
    • 4.6.2 Clock Domains

      69
      • 4.6.2.1 Clock Domain Descriptions

        69
      • 4.6.2.2 Mapping of Clock Domains to Device Modules

        71
      • 4.6.2.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC

        72
    • 4.6.3 Clock Test Mode

      73
  • 4.7 Clock Monitoring

    74
    • 4.7.1 Clock Monitor Timings

      74
    • 4.7.2 External Clock (ECLK) Output Functionality

      74
    • 4.7.3 Dual Clock Comparators

      74
      • 4.7.3.1 Features

        74
      • 4.7.3.2 Mapping of DCC Clock Source Inputs

        75
  • 4.8 Glitch Filters

    76
  • 4.9 Device Memory Map

    77
    • 4.9.1 Memory Map Diagram

      77
    • 4.9.2 Memory Map Table

      78
    • 4.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts

      82
    • 4.9.4 Master/Slave Access Privileges

      82
    • 4.9.5 Special Notes on Accesses to Certain Slaves

      82
    • 4.9.6 Parameter Overlay Module (POM) Considerations

      82
  • 4.10 Flash Memory

    84
    • 4.10.1 Flash Memory Configuration

      84
    • 4.10.2 Main Features of Flash Module

      84
    • 4.10.3 ECC Protection for Flash Accesses

      85
    • 4.10.4 Flash Access Speeds

      85
    • 4.10.5 Program Flash

      86
    • 4.10.6 Data Flash

      86
  • 4.11 Tightly-Coupled RAM Interface Module

    87
    • 4.11.1 Features

      87
    • 4.11.2 TCRAMW ECC Support

      87
  • 4.12  Parity Protection for Accesses to peripheral RAMs

    87
  • 4.13 On-Chip SRAM Initialization and Testing

    89
    • 4.13.1 On-Chip SRAM Self-Test Using PBIST

      89
      • 4.13.1.1 Features

        89
      • 4.13.1.2 PBIST RAM Groups

        89
    • 4.13.2 On-Chip SRAM Auto Initialization

      90
  • 4.14 External Memory Interface (EMIF)

    91
    • 4.14.1 Features

      91
    • 4.14.2 Electrical and Timing Specifications

      91
      • 4.14.2.1 Asynchronous RAM

        91
      • 4.14.2.2 Synchronous Timing

        96
  • 4.15 Vectored Interrupt Manager

    99
    • 4.15.1 VIM Features

      99
    • 4.15.2 Interrupt Request Assignments

      99
  • 4.16 DMA Controller

    103
    • 4.16.1 DMA Features

      103
    • 4.16.2 Default DMA Request Map

      104
  • 4.17 Real Time Interrupt Module

    106
    • 4.17.1 Features

      106
    • 4.17.2 Block Diagrams

      106
    • 4.17.3 Clock Source Options

      107
    • 4.17.4 Network Time Synchronization Inputs

      107
  • 4.18 Error Signaling Module

    108
    • 4.18.1 Features

      108
    • 4.18.2 ESM Channel Assignments

      108
  • 4.19 Reset / Abort / Error Sources

    112
  • 4.20 Digital Windowed Watchdog

    115
  • 4.21 Debug Subsystem

    116
    • 4.21.1 Block Diagram

      116
    • 4.21.2 Debug Components Memory Map

      116
    • 4.21.3 JTAG Identification Code

      116
    • 4.21.4 Debug ROM

      116
    • 4.21.5 JTAG Scan Interface Timings

      118
    • 4.21.6 Advanced JTAG Security Module

      119
    • 4.21.7 Boundary Scan Chain

      120
• 5 Peripheral Information and Electrical Specifications

  121
  • 5.1 Enhanced Translator PWM Modules (ePWM)

    121
    • 5.1.1 ePWM Clocking and Reset

      122
    • 5.1.2 Synchronization of ePWMx Time Base Counters

      122
    • 5.1.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base

      122
    • 5.1.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules

      123
    • 5.1.5 ePWM Synchronization with External Devices

      123
    • 5.1.6 ePWM Trip Zones

      123
      • 5.1.6.1 Trip Zones TZ1n, TZ2n, TZ3n

        123
      • 5.1.6.2 Trip Zone TZ4n

        123
      • 5.1.6.3 Trip Zone TZ5n

        124
      • 5.1.6.4 Trip Zone TZ6n

        124
    • 5.1.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs

      124
    • 5.1.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings

      124
  • 5.2 Enhanced Capture Modules (eCAP)

    126
    • 5.2.1 Clock Enable Control for eCAPx Modules

      126
    • 5.2.2 PWM Output Capability of eCAPx

      127
    • 5.2.3 Input Connection to eCAPx Modules

      127
    • 5.2.4 Enhanced Capture Module (eCAP) Timings

      127
  • 5.3 Enhanced Quadrature Encoder (eQEP)

    128
    • 5.3.1 Clock Enable Control for eQEPx Modules

      128
    • 5.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs

      128
    • 5.3.3 Input Connections to eQEPx Modules

      128
    • 5.3.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing

      129
  • 5.4 Multi-Buffered 12bit Analog-to-Digital Converter

    130
    • 5.4.1 Features

      130
    • 5.4.2 Event Trigger Options

      130
      • 5.4.2.1 MIBADC1 Event Trigger Hookup

        130
      • 5.4.2.2 MIBADC2 Event Trigger Hookup

        131
      • 5.4.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules

        132
    • 5.4.3 ADC Electrical and Timing Specifications

      135
    • 5.4.4 Performance (Accuracy) Specifications

      138
      • 5.4.4.1 MibADC Nonlinearity Errors

        138
      • 5.4.4.2 MibADC Total Error

        140
  • 5.5 General-Purpose Input/Output

    141
    • 5.5.1 Features

      141
  • 5.6 Enhanced High-End Timer (N2HET)

    142
    • 5.6.1 Features

      142
    • 5.6.2 N2HET RAM Organization

      142
    • 5.6.3 Input Timing Specifications

      142
    • 5.6.4 N2HET1-N2HET2 Synchronization

      143
    • 5.6.5 N2HET Checking

      143
      • 5.6.5.1 Internal Monitoring

        143
      • 5.6.5.2 Output Monitoring using Dual Clock Comparator (DCC)

        143
    • 5.6.6 Disabling N2HET Outputs

      144
    • 5.6.7 High-End Timer Transfer Unit (HTU)

      145
      • 5.6.7.1 Features

        145
      • 5.6.7.2 Trigger Connections

        145
  • 5.7 Controller Area Network (DCAN)

    146
    • 5.7.1 Features

      146
    • 5.7.2 Electrical and Timing Specifications

      146
  • 5.8 Local Interconnect Network Interface (LIN)

    147
    • 5.8.1 LIN Features

      147
  • 5.9 Serial Communication Interface (SCI)

    148
    • 5.9.1 Features

      148
  • 5.10 Inter-Integrated Circuit (I2C)

    149
    • 5.10.1 Features

      149
    • 5.10.2 I2C I/O Timing Specifications

      150
  • 5.11 Multi-Buffered / Standard Serial Peripheral Interface

    152
    • 5.11.1 Features

      152
    • 5.11.2 MibSPI Transmit and Receive RAM Organization

      152
    • 5.11.3 MibSPI Transmit Trigger Events

      152
      • 5.11.3.1 MIBSPI1 Event Trigger Hookup

        153
      • 5.11.3.2 MIBSPI3 Event Trigger Hookup

        153
      • 5.11.3.3 MIBSPI5 Event Trigger Hookup

        154
    • 5.11.4 MibSPI/SPI Master Mode I/O Timing Specifications

      156
    • 5.11.5 SPI Slave Mode I/O Timings

      160
  • 5.12 Ethernet Media Access Controller

    164
    • 5.12.1 Ethernet MII Electrical and Timing Specifications

      164
    • 5.12.2 Ethernet RMII Timing

      166
    • 5.12.3 Management Data Input/Output (MDIO)

      167
  • 5.13 Universal Serial Bus Controller

    168
    • 5.13.1 Features

      168
    • 5.13.2 Electrical and Timing Specifications

      168
• 6 Device and Documentation Support

  170
  • 6.1 Device and Development-Support Tool Nomenclature

    170
  • 6.2 Community Resources

    170
  • 6.3 Device Identification

    171
    • 6.3.1 Device Identification Code Register

      171
    • 6.3.2 Die Identification Registers

      172
  • 6.4 Module Certifications

    173
    • 6.4.1 DCAN Certification

      174
    • 6.4.2 LIN Certification

      175
      • 6.4.2.1 LIN Master Mode

        175
      • 6.4.2.2 LIN Slave Mode - Fixed Baud Rate

        176
      • 6.4.2.3 LIN Slave Mode - Adaptive Baud Rate

        177
• 7 Mechanical Data

  178
  • 7.1 Thermal Data

    178
  • 7.2 Packaging Information

    178