Texas Instruments DDC11XEVM-PDK - DDC11xEVM-PDK Evaluation Module DDC11XEVM-PDK DDC11XEVM-PDK Datenbogen
Produktcode
DDC11XEVM-PDK
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DDC11xEVM-PDK Kit Operation
•
FORMAT: Choose how many bits wide the output word is on the DOUT line (16- or 20-bit). This option
does not correspond to the FORMAT pin on the DDC114. It only controls the FPGA, and should be left
at 20 bits for the DDC112 for proper operation.
does not correspond to the FORMAT pin on the DDC114. It only controls the FPGA, and should be left
at 20 bits for the DDC112 for proper operation.
•
Channel Count: Number of channels to read back. Only the 2 or 4 settings are valid for the DDC112
or DDC114.
or DDC114.
•
DCLK (High) (Low): The number of master clock cycles for DCLK to remain low and high during data
readback. DCLK can be faster than the DDC System Clock, which is why DCLK is separate and may
be much smaller than CLK Count.
readback. DCLK can be faster than the DDC System Clock, which is why DCLK is separate and may
be much smaller than CLK Count.
•
nDVALID Ignore: This is the number of nDVALID pulses to ignore, or rather the number of samples to
initially discard from the device. Setting this number higher can help negate the effects of settling and
give cleaner data from a dead conversion stop.
initially discard from the device. Setting this number higher can help negate the effects of settling and
give cleaner data from a dead conversion stop.
•
nDVALID Read: This is the number of nDVALID pulses after which to capture data. The device has
two sides to each integrator, so if there is a 4-channel device, 256 nDVALID Reads equate to 128
samples on four channels of both A and B sides.
two sides to each integrator, so if there is a 4-channel device, 256 nDVALID Reads equate to 128
samples on four channels of both A and B sides.
•
DCLK Wait: This is the number of master clock cycles to wait after detecting an nDVALID signal. Once
a signal is detected, the data are ready; in some applications, however, a delay is helpful in achieving
desired results.
a signal is detected, the data are ready; in some applications, however, a delay is helpful in achieving
desired results.
•
HARDWARE TRIGGER: In normal operation, this should be Disabled. If Enabled, a pulse can be
issued on IP_1 to start a conversion after Take Data is pressed. If enabled and no pulse ever comes,
the program appears to be frozen. If this condition happens, disable, cancel out the error messages,
and refresh.
issued on IP_1 to start a conversion after Take Data is pressed. If enabled and no pulse ever comes,
the program appears to be frozen. If this condition happens, disable, cancel out the error messages,
and refresh.
The Write button sends data from the PC to the FPGA, programming the settings in the FPGA to
correspond to the settings listed above. When this button is pressed, the data are written and read back. If
the data read back equal the data written, the screen appears as normal; however, if the data read back is
different than the data set in the fields above, the text in those fields appears in a different color than black
(on most systems, it appears in a dark red color).
correspond to the settings listed above. When this button is pressed, the data are written and read back. If
the data read back equal the data written, the screen appears as normal; however, if the data read back is
different than the data set in the fields above, the text in those fields appears in a different color than black
(on most systems, it appears in a dark red color).
7.3.3.2
Device Configuration Group Box
The controls in this box set the state of device configuration bits on the selected device under test, and
correspond to those pins directly.
correspond to those pins directly.
•
Range[2:0]: These check boxes correspond to the RANGE pins on the DDC devices, and configure
the range that the DDC is in. Checked corresponds to a logic 1; unchecked is a logic 0. '000' is range 0
and '111' is range 7, etc.
the range that the DDC is in. Checked corresponds to a logic 1; unchecked is a logic 0. '000' is range 0
and '111' is range 7, etc.
•
Format: (DDC114 only) This configures the format that the DDC114 outputs data. '1' is 20-bit data per
channel; '0' is 16-bit data.
channel; '0' is 16-bit data.
•
SPEED: This configures the Power setting for the DDC114. Unchecked ('0') is low speed and checked
('1') is high speed.
('1') is high speed.
•
Testmode: This configures the test mode for the DDC. Unchecked ('0') turns TEST mode off, and
checked ('1') is TEST mode on. TEST mode disconnects the inputs and should produce an ideal
baseline for noise and offset in the system.
checked ('1') is TEST mode on. TEST mode disconnects the inputs and should produce an ideal
baseline for noise and offset in the system.
Pressing the Write to Pins button sets the corresponding device hardware pins to the states in the
checkboxes.
checkboxes.
7.3.3.3
Direct DDC Control Group Box
The Hard Reset DDC button applies an approximately 500ms long pulse to the nRESET pin on the DDC,
resetting the device.
resetting the device.
21
SLAU234A – October 2007 – Revised July 2010
DDC11xEVM-PDK User's Guide
Copyright © 2007–2010, Texas Instruments Incorporated