Texas Instruments DAC8728EVM - DAC8728 Evaluation Module DAC8728EVM DAC8728EVM Datenbogen
Produktcode
DAC8728EVM
SN74LVC1G32
WE
Latch
Latch_CTRL
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Parallel Control
Also, in order to appropriately control the CLK input to the SN74LVC374 (U11), the LATCH_CTRL output
of the SN74LVC139 (U7) had to be logic ORed with the WE signal. This configuration ensures that the
data are latched into the SN74LVC374 while it is still valid from the DSP. This circuit and related truth
table (
of the SN74LVC139 (U7) had to be logic ORed with the WE signal. This configuration ensures that the
data are latched into the SN74LVC374 while it is still valid from the DSP. This circuit and related truth
table (
and
, respectively) can be seen below.
Figure 3. LATCH External Logic
Table 4. SN74LVC374 Control
LATCH_CTRL
WE
LATCH
0
0
0
0
1
1
1
0
1
1
1
1
The final piece of external logic gives the EVM user the ability to control the LDAC signal from both the
processor I/O pins and the SN74LVC139 (U7) output. This control is achieved through an AND gate that
uses the EXT_LDAC signal and the LDAC_CTRL signal to drive the input on the DAC8728. The interrupt
service routine toggles the EXT_LDAC signal and then waits for the next interrupt.
processor I/O pins and the SN74LVC139 (U7) output. This control is achieved through an AND gate that
uses the EXT_LDAC signal and the LDAC_CTRL signal to drive the input on the DAC8728. The interrupt
service routine toggles the EXT_LDAC signal and then waits for the next interrupt.
displays the
behavior of the logic.
Table 5. LDAC Control
EXT_LDAC
LDAC_CTRL
LDAC
0
0
0
0
1
0
1
0
0
1
1
1
7
SBAU161 – February 2010
DAC8728EVM
Copyright © 2010, Texas Instruments Incorporated