Texas Instruments DAC8728EVM - DAC8728 Evaluation Module DAC8728EVM DAC8728EVM Datenbogen
Produktcode
DAC8728EVM
V
CC
Y
A
B
GND
SN74LVC1G32
OR Gate
IOVDD
U5
5
4
1
2
3
3
Latch_CTRL
WE
Latch
V
CC
Y
A
B
GND
SN74LVC1G32
OR Gate
IOVDD
IOVDD
IOVDD
IOVDD
U6
5
4
1
2
3
3
DC_CS
CS
CE
V
CC
Y
A
B
GND
SN74LVC1G08
AND Gate
IOVDD
U8
5
4
1
2
3
3
RE
WE
WE
RE
1Y0
1A
1G
2Y0
1Y1
1B
2G
2A
2B
2B
2Y1
1Y2
2Y2
1Y3
2Y3
U7
V
C
C
GND
2
4
6
13
15
14
1
3
5
7
12
10
11
9
SN74LVS139A
6
4
2
8
10
12
14
16
20
18
5
3
1
7
9
11
13
15
19
17
Parallel Control
J1
CE
BUSY
Ext_LDAC
EVM_A3
EVM_A2
EVM_A1
EVM_A0
Latch_CTRL
R/W
1
DC_CS
JP10
Jumper
CS
LDAC_CTRL
JP9
Jumper
RST
JP3
Jumper
CLR
R9
10kW
R6
10kW
RST
CLR
SN74LVC1G32
SN74LVC1G08
WE
RE
DC CS
CS
Parallel Control
www.ti.com
shows the parallel control header and the connections to the SN74LVC139.
Figure 1. Parallel Control Header and SN74LVC139
4.1
Required External Logic
Most of TI’s host processors do not have a hardware chip select that meets the timing requirements of the
DAC8728. Therefore, external logic was added to the EVM to create an acceptable CS signal for the DAC
using the WE, RE, and DC_CS signals. This circuit and related truth table are shown in this section.
DAC8728. Therefore, external logic was added to the EVM to create an acceptable CS signal for the DAC
using the WE, RE, and DC_CS signals. This circuit and related truth table are shown in this section.
and
illustrate the external logic behavior.
Figure 2. Chip-Select External Logic
As you can see from the timing diagram, the CS line never goes low unless the DC_CS signal and either
WE or RE is low as well.
WE or RE is low as well.
Table 3. External Logic Behavior
DC_CS
WE
RE
CS
0
0
0
Not a valid DSP output
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
6
DAC8728EVM
SBAU161 – February 2010
Copyright © 2010, Texas Instruments Incorporated