Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE Datenbogen
Produktcode
TMDSEVM6472LE
PRODUCTPREVIEW
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
corresponding C64x+ megamodule. This transition causes the Boot Controller to bring the C64x+
megamodule core out of the "held-in-reset" state. The CPU then begins execution from the internal L2
SRAM address programmed in the DSP_BOOT_ADDRx register. All memory may be written to and
read by the host. This allows for the host to verify what it sends to the DSP, if required.
megamodule core out of the "held-in-reset" state. The CPU then begins execution from the internal L2
SRAM address programmed in the DSP_BOOT_ADDRx register. All memory may be written to and
read by the host. This allows for the host to verify what it sends to the DSP, if required.
For the C6472 device, only the Host Port Interface (HPI) peripheral can be used for host boot. PLL1,
which provides CPU/6 clock to the HPI module, will initially be running in bypass mode. Therefore, the
HPI interface will be very slow and HRDY must be observed. Initial HPI accesses can configure PLL1
for full-speed operation to make HPI accesses shorter.
which provides CPU/6 clock to the HPI module, will initially be running in bypass mode. Therefore, the
HPI interface will be very slow and HRDY must be observed. Initial HPI accesses can configure PLL1
for full-speed operation to make HPI accesses shorter.
•
Master I2C boot
After global reset, the C64x+ megamodule core 0 comes out of RESET and starts executing the
shared ROM code from the address provided by the Boot Controller based on the I2C boot mode
selection. Then C64x+ megamodule core 0 configures I2C and acts as a master to the I2C bus and
copies data from an I2C EPROM or a device acting as an I2C slave to the DSP using a predefined
boot table format. The destination address and length are contained within the boot table. After
initializing the on-chip memory to the known state and initializing the start address of the other C64x+
megamodule cores, C64x+ megamodule core 0 brings the other cores out of reset by writing a 1 to bit
fields BC1 through BC5 of the BOOT_COMPLETE_STAT register. After this, C64x+ megamodule
cores 1 through 5 start executing from the start address provided by C64x+ megamodule core 0.
shared ROM code from the address provided by the Boot Controller based on the I2C boot mode
selection. Then C64x+ megamodule core 0 configures I2C and acts as a master to the I2C bus and
copies data from an I2C EPROM or a device acting as an I2C slave to the DSP using a predefined
boot table format. The destination address and length are contained within the boot table. After
initializing the on-chip memory to the known state and initializing the start address of the other C64x+
megamodule cores, C64x+ megamodule core 0 brings the other cores out of reset by writing a 1 to bit
fields BC1 through BC5 of the BOOT_COMPLETE_STAT register. After this, C64x+ megamodule
cores 1 through 5 start executing from the start address provided by C64x+ megamodule core 0.
•
Slave I2C boot
A Slave I2C boot is also implemented, which programs the DSP as an I2C slave. A DSP in I2C slave
mode will never transmit on the I2C bus. The slave DSP must first receive a three-word transmission
from the master. This transmission includes a 16-bit length field (length is in bytes, should be 6 for this
block), a 16-bit checksum field for which a value of zero means ignore the checksum, and the 16-bit
options field described in the boot parameter table for standard I2C boot. This option field informs the
slave what information is contained in the next data blocks. Typically, the option field is set to 1 to
indicate boot tables will be received next. Only core 0 is active during the boot process. Using the
slave I2C boot, a single DSP or device acting as an I2C master can simultaneously boot multiple slave
DSPs connected to the same I2C bus. Note that the master DSP may require booting via an I2C
EEPROM before acting as a master and booting other DSPs.
mode will never transmit on the I2C bus. The slave DSP must first receive a three-word transmission
from the master. This transmission includes a 16-bit length field (length is in bytes, should be 6 for this
block), a 16-bit checksum field for which a value of zero means ignore the checksum, and the 16-bit
options field described in the boot parameter table for standard I2C boot. This option field informs the
slave what information is contained in the next data blocks. Typically, the option field is set to 1 to
indicate boot tables will be received next. Only core 0 is active during the boot process. Using the
slave I2C boot, a single DSP or device acting as an I2C master can simultaneously boot multiple slave
DSPs connected to the same I2C bus. Note that the master DSP may require booting via an I2C
EEPROM before acting as a master and booting other DSPs.
•
Ethernet MAC boot
When BOOTMODE [3:0] = 1001 is selected, Ethernet MAC boot is initiated on EMAC0 with the mode
specified by the MACSEL0[2:0] pins. Alternately, when BOOTMODE [3:0] = 1010 is selected, Ethernet
MAC boot is initiated on EMAC1 with the mode specified by the MACSEL1[1:0] pins.
specified by the MACSEL0[2:0] pins. Alternately, when BOOTMODE [3:0] = 1010 is selected, Ethernet
MAC boot is initiated on EMAC1 with the mode specified by the MACSEL1[1:0] pins.
After reset, the C64x+ megamodule core 0 comes out of RESET and starts executing the shared ROM
code from the address provided by the Boot Controller based on the Ethernet boot mode selection
(1001b or 1010b). The C64x+ megamodule core 0 configures the appropriate Ethernet MAC and
brings the code image into the on-chip memory via the protocol defined. After initializing the on-chip
memory to the known state and initializing the start address of the other C64x+ megamodule cores (1
through 5), C64x+ megamodule core 0 brings the other cores out of reset by writing a 1 to bit fields
BC1 through BC5 of the BOOT_COMPLETE_STAT register. After this, C64x+ megamodule cores 1
through 5 start executing from the start address provided by C64x+ megamodule core 0.
code from the address provided by the Boot Controller based on the Ethernet boot mode selection
(1001b or 1010b). The C64x+ megamodule core 0 configures the appropriate Ethernet MAC and
brings the code image into the on-chip memory via the protocol defined. After initializing the on-chip
memory to the known state and initializing the start address of the other C64x+ megamodule cores (1
through 5), C64x+ megamodule core 0 brings the other cores out of reset by writing a 1 to bit fields
BC1 through BC5 of the BOOT_COMPLETE_STAT register. After this, C64x+ megamodule cores 1
through 5 start executing from the start address provided by C64x+ megamodule core 0.
•
Serial RapidIO boot
After reset, the C64x+ megamodule core 0 comes out of RESET and starts executing the shared ROM
code from the address provided by the Boot Controller based on the Serial RapidIO boot mode
selection (1011b, 1100b, 1101b, or 1110b). The C64x+ megamodule core 0 configures Serial RapidIO
and EDMA, if required, and brings the code image into the on-chip memory via the protocol defined by
the boot method (SRIO bootloader). After initializing the on-chip memory to the known state and
initializing the start address of the other C64x+ megamodule cores (1 through 5), C64x+ megamodule
core 0 brings the other cores out of reset by writing a 1 to bit fields BC1 through BC5 of the
BOOT_COMPLETE_STAT register. After this, the C64x+ megamodule cores 1 through 5 start
executing from the start address provided by C64x+ megamodule core 0.
code from the address provided by the Boot Controller based on the Serial RapidIO boot mode
selection (1011b, 1100b, 1101b, or 1110b). The C64x+ megamodule core 0 configures Serial RapidIO
and EDMA, if required, and brings the code image into the on-chip memory via the protocol defined by
the boot method (SRIO bootloader). After initializing the on-chip memory to the known state and
initializing the start address of the other C64x+ megamodule cores (1 through 5), C64x+ megamodule
core 0 brings the other cores out of reset by writing a 1 to bit fields BC1 through BC5 of the
BOOT_COMPLETE_STAT register. After this, the C64x+ megamodule cores 1 through 5 start
executing from the start address provided by C64x+ megamodule core 0.
•
UTOPIA boot
Copyright
©
2009
–
2011, Texas Instruments Incorporated
Device Overview
17
Product Folder Link(s) :