Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE Datenbogen
Produktcode
TMDSEVM6472LE
PRODUCTPREVIEW
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
After reset, the C64x+ megamodule core 0 comes out of RESET and starts executing the shared ROM
code from the address provided by the Boot Controller based on the UTOPIA boot mode selection
(0101b, 0110b, 0111b, 1000b). The C64x+ megamodule core 0 configures the UTOPIA and brings the
code image into the on-chip memory via the protocol defined. After initializing the on-chip memory to
the known state and initializing the start address of the other C64x+ megamodule cores (1 through 5),
C64x+ megamodule core 0 brings the other cores out of reset by writing a 1 to bit fields ofBC1 through
BC5 the BOOT_COMPLETE_STAT register. After this, C64x+ megamodule cores 1 through 5 start
executing from the start address provided by C64x+ megamodule core 0.
code from the address provided by the Boot Controller based on the UTOPIA boot mode selection
(0101b, 0110b, 0111b, 1000b). The C64x+ megamodule core 0 configures the UTOPIA and brings the
code image into the on-chip memory via the protocol defined. After initializing the on-chip memory to
the known state and initializing the start address of the other C64x+ megamodule cores (1 through 5),
C64x+ megamodule core 0 brings the other cores out of reset by writing a 1 to bit fields ofBC1 through
BC5 the BOOT_COMPLETE_STAT register. After this, C64x+ megamodule cores 1 through 5 start
executing from the start address provided by C64x+ megamodule core 0.
After local resets, the C6472 device supports two boot modes via BOOTMODE0-BOOTMODE5
device-level registers:
device-level registers:
•
Immediate boot
When immediate boot is selected after global reset, the C64x+ megamodule core (x) executes directly
from the internal L2 SRAM address programmed in the DSP_BOOT_ADDRx register upon being given
a local reset. Note: device operation is undefined if invalid code is address programmed in the
DSP_BOOT_ADDRx register. Executing invalid code may prevent connection by an emulator.
from the internal L2 SRAM address programmed in the DSP_BOOT_ADDRx register upon being given
a local reset. Note: device operation is undefined if invalid code is address programmed in the
DSP_BOOT_ADDRx register. Executing invalid code may prevent connection by an emulator.
•
Host boot
If host boot is selected after global reset, the C64x+ megamodule core (x) is internally "held in reset"
while the remainder of the C64x+ megamodule is released from reset upon being given a local reset.
During this period, an external host can initialize the C64x+ megamodule (x) memory space, as
necessary, through an HPI interface. Once the host is finished with all necessary initialization, it must
write a 1 to the corresponding bit field BCx of the BOOT_COMPLETE_STAT register (inside the Boot
Controller) indicating boot complete of the corresponding C64x+ megamodule. This transition causes
the Boot Controller to bring the C64x+ megamodule core out of the "held-in-reset" state. The core (x)
then begins execution from the internal L2 SRAM programmed in the DSP_BOOT_ADDRx register. All
memory may be written to and read by the host. This allows for the host to verify what it sends to the
DSP, if required.
while the remainder of the C64x+ megamodule is released from reset upon being given a local reset.
During this period, an external host can initialize the C64x+ megamodule (x) memory space, as
necessary, through an HPI interface. Once the host is finished with all necessary initialization, it must
write a 1 to the corresponding bit field BCx of the BOOT_COMPLETE_STAT register (inside the Boot
Controller) indicating boot complete of the corresponding C64x+ megamodule. This transition causes
the Boot Controller to bring the C64x+ megamodule core out of the "held-in-reset" state. The core (x)
then begins execution from the internal L2 SRAM programmed in the DSP_BOOT_ADDRx register. All
memory may be written to and read by the host. This allows for the host to verify what it sends to the
DSP, if required.
2.4.2
BOOTACTIVE
The output pin, BOOTACTIVE, is asserted upon reset and de-asserted on boot complete. In the case of
BOOTMODE 0, all cores are released from reset immediately. BOOTACTIVE also goes low within a small
number of cycles, as all cores are out of reset and running. In the case of BOOTMODE 1, the host needs
to write to the boot complete bit in the BOOT_COMPLETE_STAT register corresponding to each C64x+
megamodule that is to be taken out of reset. BOOTACTIVE will be high if any cores are held in reset. In
the case of any other boot, core 0 comes out of RESET immediately, but all other cores are still in
RESET,
BOOTMODE 0, all cores are released from reset immediately. BOOTACTIVE also goes low within a small
number of cycles, as all cores are out of reset and running. In the case of BOOTMODE 1, the host needs
to write to the boot complete bit in the BOOT_COMPLETE_STAT register corresponding to each C64x+
megamodule that is to be taken out of reset. BOOTACTIVE will be high if any cores are held in reset. In
the case of any other boot, core 0 comes out of RESET immediately, but all other cores are still in
RESET,
so
BOOTACTIVE
will
be
high.
The
ROM
code
will
not
write
to
either
the
BOOT_COMPLETE_STAT or the BOOT_ADDRESS register unless explicitly directed to do so by the data
provided in the boot process. Any active core can set bits in BOOT_COMPLETE_STAT at any time to
begin code execution on inactive cores. BOOTACTIVE will go low after the boot complete bit (BCx) in the
BOOT_COMPLETE_STAT register is set for all six cores. For a detailed explanation of this operation, see
the TMS320C645x/C647x Bootloader User's Guide (literature number
provided in the boot process. Any active core can set bits in BOOT_COMPLETE_STAT at any time to
begin code execution on inactive cores. BOOTACTIVE will go low after the boot complete bit (BCx) in the
BOOT_COMPLETE_STAT register is set for all six cores. For a detailed explanation of this operation, see
the TMS320C645x/C647x Bootloader User's Guide (literature number
18
Device Overview
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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