Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE Datenbogen
Produktcode
TMDSEVM6472LE
PRODUCTPREVIEW
2
3
TX_CLK
TX_SYNC
TX_DATA
1
1
2
5
RX_CLK
RX_SYNC
RX_DATA
3
4
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
7.15.4.4 EMAC SSMII Electrical Data/Timing
Table 7-122. Timing Requirements for EMAC SSMII Transmit
(see
500/625/700
NO.
PARAMETER
UNIT
MIN
TYP
MAX
1
t
c(TX_CLK)
Cycle time, TX_CLK
8
ns
t
d(TX_CLK-
2
Delay time, TX_CLK high to TX_SYNC output valid
0.5
4.5
ns
TX_SYNC)
t
d(TX_CLK-
3
Delay time, TX_CLK high to TX_DATA output valid
0.5
4.5
ns
TX_DATA)
Figure 7-56. SSMII Transmit Timing
Table 7-123. Timing Requirements for EMAC SSMII Receive
(see
500/625/700
NO.
PARAMETER
UNIT
MIN
TYP
MAX
1
t
c(TR_CLK)
Cycle time, TR_CLK
8
ns
2
t
su(RX_SYNC)
Setup time, RX_SYNC setup time
1.5
ns
3
t
h(RX_SYNC)
Hold time, RX_SYNC hold time
1
ns
4
t
su(RX_DATA)
Setup time, RX_DATA setup time
1.5
ns
5
t
h(RX_DATA)
Hold time, RX_DATA hold time
1
ns
Figure 7-57. SSMII Receive Timing
234
C64x+ Peripheral Information and Electrical Specifications
Copyright
©
2009
–
2011, Texas Instruments Incorporated
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