Texas Instruments F28M36 Concerto Control Card TMDSCNCD28M36 TMDSCNCD28M36 Datenbogen
Produktcode
TMDSCNCD28M36
C9-C15
RAM
7 x 8 KB
(parity)
C2-C8
RAM
7 x 8 KB
(parity)
SECURE
FLASH
1 MB
(ECC)
(ECC)
BOOT
ROM
64 KB
GPIO_MUX1
G
P
T
IM
E
R
(4
(4
)
u
C
R
C
I
C
(2
(2
)
2
S
S
I
(4
)
U
A
R
T
(5
(5
)
U
S
B
+
P
H
Y
(O
T
G
)
E
M
A
C
W
D
D
O
G
(2
(2
)
N
M
I
W
D
D
O
G
SECURE
C1
RAM
8 KB
(ECC)
SECURE
C0
RAM
8 KB
(ECC)
AHB BUS
APB BUS
S0-S7 SHARED RAM (parity)
S0
8 KB
S1
8 KB
S2
8 KB
S3
8 KB
S4
8 KB
S5
8 KB
S6
8 KB
S7
8 KB
MTOC
MSG
RAM
RAM
(parity)
2 KB
CTOM
MSG
RAM
RAM
(parity)
2 KB
IPC
INTER-
PROC
COMM
M3 SYSTEM BUS
uDMA BUS
L3
RAM
8 KB
(parity)
L2
RAM
8 KB
(parity)
SECURE
FLASH
512 KB
(ECC)
BOOT
ROM
64 KB
SECURE
L1
RAM
8 KB
(ECC)
SECURE
L0
RAM
8 KB
(ECC)
T
IM
E
R
(3
(3
)
X
IN
T
(3
(3
)
E
P
W
M
(1
M
(1
2
)
N
M
I
W
D
D
O
G
E
Q
E
P
(3
(3
)
E
C
A
P
(6
(6
)
M
cB
S
P
I
C
2
S
C
I
S
P
I
GPIO_MUX1
M1
RAM
2 KB
(ECC)
M0
RAM
2 KB
(ECC)
C28 CPU BUS
C28 DMA BUS
16-
BIT
BIT
PF2
32-
BIT
BIT
PF1
32-
BIT
BIT
PF3
C28 CPU
C28
FPU
C28
VCU
C28
DMA
M3 CPU
NVIC
MPU
M3
BUS
MATRIX
M3
uDMA
I-CODE BUS
D-CODE BUS
136 PINS
REGS
ONLY
ONLY
PIE
ADC_1
MODULE
ADC_2
MODULE
G
P
IO
_
M
U
X
2
1
2
P
IN
S
A
IO
_
M
U
X
2
A
IO
_
M
U
X
1
1
2
P
IN
S
16/32
- BIT
PF0
8
P
IN
S
ANALOG
SUBSYSTEM
6
COMP
INPUTS
6
COMP
INPUTS
12
ADC
INPUTS
6
COMP
OUT
PUTS
12
ADC
INPUTS
6
COMPARE
+ DAC
UNITS
UNITS
MEM32
TO AHB
BUS
BRIDGE
A
N
A
LO
G
C
C
O
M
M
O
N
IN
IN
T
E
R
F
A
C
E
B
B
U
S
1.2V
VREG
1.8V
VREG
C28 CPU/DMA
ACCESS TO EPI
ACCESS TO EPI
E
P
I
INTER-
PROC
COMM
C
A
N
(2
(2
)
RESETS
NMI
CLOCKS
SECURITY
DEBUG
FREQ
GASKET
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
1.4
Functional Block Diagram
Figure 1-1. Functional Block Diagram
Copyright © 2012–2014, Texas Instruments Incorporated
Device Summary
3
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