Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 Datenbogen
Produktcode
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
Table 6-20. Master Subsystem – Flash Parameters at 125 MHz
(1) (2)
TEST
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
Program Time
(3)
128 bits
240
μs
32K Sector
500
ms
128K Sector
2000
ms
Erase Time
32K Sector
50
ms
128K Sector
50
ms
(1)
The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2)
Erase time includes Erase verify by the CPU.
(3)
Program time includes overhead of state machine but does not include data transfer time. Program time assumes programming 144 bits
at a time. Program time includes Program verify by the CPU.
at a time. Program time includes Program verify by the CPU.
Table 6-21. Master Subsystem – Flash/OTP Access Timing
(1)
PARAMETER
MIN
MAX
UNIT
t
a(f)
Flash access time
25
ns
t
a(OTP)
OTP access time
50
ns
(1)
Access time numbers shown in this table are prior to device characterization. Final numbers will be published in the datasheet for the
fully qualified production device.
fully qualified production device.
Table 6-22. Master Subsystem – Flash Data Retention Duration
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t
retention
Data retention duration
T
J
= 85°C
20
years
140
Electrical Specifications
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