Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 Datenbogen
Produktcode
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
3.5.3
Analog Comparator + DAC
There are six Comparator blocks enabling simultaneous comparison of multiple pairs of analog inputs,
resulting in six digital comparison outputs. The external analog inputs that are being compared in the
comparators come from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared
against each other or the outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual
Comparator modules. The six comparator outputs go to the GPIO_MUX2 block where they can be
mapped to six out of eight available pins.
resulting in six digital comparison outputs. The external analog inputs that are being compared in the
comparators come from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared
against each other or the outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual
Comparator modules. The six comparator outputs go to the GPIO_MUX2 block where they can be
mapped to six out of eight available pins.
Note that in order to use these comparator outputs to trip the C28x EPWMA/B outputs, they must be first
routed externally from pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before
they can be assigned to selected 12 ePWM Trip Inputs.
routed externally from pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before
they can be assigned to selected 12 ePWM Trip Inputs.
See
for more information on the analog comparator + DAC.
3.5.4
Analog Common Interface Bus
The ACIB links the Master and Control Subsystems with the Analog Subsystem. The ACIB enables the
Cortex-M3 CPU/µDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC Triggers
to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The Cortex-M3
uses its System Bus and the µDMA Bus to read from ADC Result registers. The C28x uses its Memory
Bus and the DMA bus to access ADC Result registers and other registers of the Analog Subsystem. The
ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the Master/Control
Subsystem side of ACIB to access the ADC and Analog Comparator registers on the Analog Subsystem
side.
Cortex-M3 CPU/µDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC Triggers
to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The Cortex-M3
uses its System Bus and the µDMA Bus to read from ADC Result registers. The C28x uses its Memory
Bus and the DMA bus to access ADC Result registers and other registers of the Analog Subsystem. The
ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the Master/Control
Subsystem side of ACIB to access the ADC and Analog Comparator registers on the Analog Subsystem
side.
Additionally, ACIB maps up to 22 SOC trigger sources from the Control Subsystem to 8 SOC trigger
destinations inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC
interrupt sources from the Analog Subsystem to 8 destinations inside the Master and Control Subsystems.
The eight ADC interrupts are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC
interrupts from ADC2. The total of 16 possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines
because it is unlikely that any application would need all 16 interrupts at the same time.
destinations inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC
interrupt sources from the Analog Subsystem to 8 destinations inside the Master and Control Subsystems.
The eight ADC interrupts are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC
interrupts from ADC2. The total of 16 possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines
because it is unlikely that any application would need all 16 interrupts at the same time.
Eight registers (TRIG1SEL–TRIG8SEL) configure eight corresponding SOC triggers to assign 1 of 22
possible trigger sources to each SOC trigger.
possible trigger sources to each SOC trigger.
There are two registers that provide status of ACIB to the Master Subsystem and to the Control
Subsystem.
Subsystem.
The Cortex-M3 can read the MCIBSTATUS register to verify that the Analog Subsystem is properly
powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and
interrupts are correctly propagating between the Master, Control, and Analog subsystems.
powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and
interrupts are correctly propagating between the Master, Control, and Analog subsystems.
The C28x can read the CCIBSTATUS register to verify that the Analog Subsystem is properly powered
up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are
correctly propagating between the Master, Control, and Analog subsystems.
up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are
correctly propagating between the Master, Control, and Analog subsystems.
34
Device Overview
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