Texas Instruments 180 to 100 Pin DIMM Adapter TMDSADAP180TO100 TMDSADAP180TO100 Datenbogen
Produktcode
TMDSADAP180TO100
SPRS825C – OCTOBER 2012 – REVISED FEBRUARY 2014
3.6
Master Subsystem NMIs
The Cortex-M3 NMI Block generates an M3NMIINT non-maskable interrupt to the Cortex-M3 CPU and an
M3NMI event to the NMI Watchdog in response to potentially critical conditions existing inside or outside
the Concerto MCU. When able to respond to the M3NMIINT interrupt, the Cortex-M3 CPU may address
the NMI condition and disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out and an
M3NMIRST reset signal is sent to the Resets block.
M3NMI event to the NMI Watchdog in response to potentially critical conditions existing inside or outside
the Concerto MCU. When able to respond to the M3NMIINT interrupt, the Cortex-M3 CPU may address
the NMI condition and disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out and an
M3NMIRST reset signal is sent to the Resets block.
The inputs to the Cortex-M3 NMI block include the C28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR,
EXTGPIO, MLBISTERR, and CLBISTERR signals. The C28NMIRST comes from the C28x NMI
Watchdog; C28NMIRST indicates that the C28x was not able to prevent the C28x NMI Watchdog counter
from counting out. PIENMIERR indicates that an error condition was generated during the NMI vector
fetch from the C28x PIE block. The CLOCKFAIL input comes from the Master Clocks Block, announcing a
missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog
Common Interface Bus. EXTGPIO comes from the GPIO_MUX1 to announce an external emergency.
MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature mismatch
error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or
signature mismatch error has been detected.
EXTGPIO, MLBISTERR, and CLBISTERR signals. The C28NMIRST comes from the C28x NMI
Watchdog; C28NMIRST indicates that the C28x was not able to prevent the C28x NMI Watchdog counter
from counting out. PIENMIERR indicates that an error condition was generated during the NMI vector
fetch from the C28x PIE block. The CLOCKFAIL input comes from the Master Clocks Block, announcing a
missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog
Common Interface Bus. EXTGPIO comes from the GPIO_MUX1 to announce an external emergency.
MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature mismatch
error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or
signature mismatch error has been detected.
The Cortex-M3 NMI block can be accessed via the Cortex-M3 NMI configuration registers—including the
MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources, clear
the flags, and force the flags to active state, respectively.
MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources, clear
the flags, and force the flags to active state, respectively.
shows the Cortex-M3 NMI and C28x NMI.
3.7
Control Subsystem NMIs
The C28x NMI Block generates a C28NMIINT non-maskable interrupt to the C28x CPU and a C28NMI
event to the C28x NMI Watchdog in response to potentially critical conditions existing inside the Concerto
MCU. When able to respond to the C28NMIINT interrupt, the C28x CPU may address the NMI condition
and disable the C28x NMI Watchdog. Otherwise, the C28x NMI Watchdog counts out and the
C28NMIRST reset signal is sent to the Resets block and the Cortex-M3 NMI Block, where the Cortex-M3
NMI Block can generate an NMI to the Cortex-M3 processor.
event to the C28x NMI Watchdog in response to potentially critical conditions existing inside the Concerto
MCU. When able to respond to the C28NMIINT interrupt, the C28x CPU may address the NMI condition
and disable the C28x NMI Watchdog. Otherwise, the C28x NMI Watchdog counts out and the
C28NMIRST reset signal is sent to the Resets block and the Cortex-M3 NMI Block, where the Cortex-M3
NMI Block can generate an NMI to the Cortex-M3 processor.
The inputs to the C28x NMI block include the CLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR,
PIENMIERR, CLBISTERR, and MLBISTERR signals. The CLOCKFAIL input comes from the Clocks
Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal
condition inside the Analog Common Interface Bus. The RAMUCERR and FLASHUNCERR announce the
occurrence of uncorrectable error conditions during access to the Flash or RAM (local or shared).
PIENMIERR indicates that an error condition was generated during NMI vector fetch from the C28x PIE
block. MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature
mismatch error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-
out or signature mismatch error has been detected.
PIENMIERR, CLBISTERR, and MLBISTERR signals. The CLOCKFAIL input comes from the Clocks
Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal
condition inside the Analog Common Interface Bus. The RAMUCERR and FLASHUNCERR announce the
occurrence of uncorrectable error conditions during access to the Flash or RAM (local or shared).
PIENMIERR indicates that an error condition was generated during NMI vector fetch from the C28x PIE
block. MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature
mismatch error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-
out or signature mismatch error has been detected.
The C28x NMI block can be accessed via the C28x NMI configuration registers—including the CNMIFLG,
CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags,
and force the flags to active state, respectively.
CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear the flags,
and force the flags to active state, respectively.
shows the Cortex-M3 NMI and C28x NMI.
Copyright © 2012–2014, Texas Instruments Incorporated
Device Overview
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