Texas Instruments AM18x eXperimenter's Kit TMDSEXP1808L TMDSEXP1808L Datenbogen
Produktcode
TMDSEXP1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-65. General Timing Requirements for SPI0 Slave Modes
(1)
1.3V, 1.2V
1.1V
1.0V
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
9
t
c(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
40
(2)
50
(2)
60
(2)
ns
10
t
w(SPCH)S
Pulse Width High, SPI0_CLK, All Slave Modes
18
22
27
ns
11
t
w(SPCL)S
Pulse Width Low, SPI0_CLK, All Slave Modes
18
22
27
ns
Polarity = 0, Phase = 0,
2P
2P
2P
to SPI0_CLK rising
Polarity = 0, Phase = 1,
Setup time, transmit data
2P
2P
2P
to SPI0_CLK rising
written to SPI before initial
12
t
su(SOMI_SPC)S
ns
clock edge from
Polarity = 1, Phase = 0,
2P
2P
2P
master.
(3) (4)
to SPI0_CLK falling
Polarity = 1, Phase = 1,
2P
2P
2P
to SPI0_CLK falling
Polarity = 0, Phase = 0,
17
20
27
from SPI0_CLK rising
Polarity = 0, Phase = 1,
17
20
27
Delay, subsequent bits valid from SPI0_CLK falling
13
t
d(SPC_SOMI)S
on SPI0_SOMI after
ns
Polarity = 1, Phase = 0,
transmit edge of SPI0_CLK
17
20
27
from SPI0_CLK falling
Polarity = 1, Phase = 1,
17
20
27
from SPI0_CLK rising
Polarity = 0, Phase = 0,
0.5S-6
0.5S-16
0.5S-20
from SPI0_CLK falling
Polarity = 0, Phase = 1,
0.5S-6
0.5S-16
0.5S-20
Output hold time,
from SPI0_CLK rising
14
t
oh(SPC_SOMI)S
SPI0_SOMI valid after
ns
Polarity = 1, Phase = 0,
receive edge of SPI0_CLK
0.5S-6
0.5S-16
0.5S-20
from SPI0_CLK rising
Polarity = 1, Phase = 1,
0.5S-6
0.5S-16
0.5S-20
from SPI0_CLK falling
Polarity = 0, Phase = 0,
1.5
1.5
1.5
to SPI0_CLK falling
Polarity = 0, Phase = 1,
1.5
1.5
1.5
Input Setup Time,
to SPI0_CLK rising
15
t
su(SIMO_SPC)S
SPI0_SIMO valid before
ns
Polarity = 1, Phase = 0,
receive edge of SPI0_CLK
1.5
1.5
1.5
to SPI0_CLK rising
Polarity = 1, Phase = 1,
1.5
1.5
1.5
to SPI0_CLK falling
Polarity = 0, Phase = 0,
4
4
5
from SPI0_CLK falling
Polarity = 0, Phase = 1,
4
4
5
Input Hold Time,
from SPI0_CLK rising
16
t
ih(SPC_SIMO)S
SPI0_SIMO valid after
ns
Polarity = 1, Phase = 0,
receive edge of SPI0_CLK
4
4
5
from SPI0_CLK rising
Polarity = 1, Phase = 1,
4
4
5
from SPI0_CLK falling
(1)
P = SYSCLK2 period; S = t
c(SPC)S
(SPI slave bit clock period)
(2)
This timing is limited by the timing shown or 3P, whichever is greater.
(3)
First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(4)
Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
Copyright © 2010–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
155
Product Folder Links: