Datenbogen (TMDSEXP1808L)Inhaltsverzeichnis1 AM1808 ARM Microprocessor11.1 Features11.2 Applications21.3 Description31.4 Functional Block Diagram4Table of Contents52 Revision History63 Device Overview73.1 Device Characteristics73.2 Device Compatibility83.3 ARM Subsystem83.3.1 ARM926EJ-S RISC CPU83.3.2 CP1583.3.3 MMU93.3.4 Caches and Write Buffer93.3.5 Advanced High-Performance Bus (AHB)93.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)103.3.7 ARM Memory Mapping103.4 Memory Map Summary113.5 Pin Assignments143.5.1 Pin Map (Bottom View)143.6 Pin Multiplexing Control173.7 Terminal Functions183.7.1 Device Reset and JTAG183.7.2 High-Frequency Oscillator and PLL193.7.3 Real-Time Clock and 32-kHz Oscillator203.7.4 DEEPSLEEP Power Control203.7.5 External Memory Interface A (EMIFA)213.7.6 DDR2/mDDR Memory Controller243.7.7 Serial Peripheral Interface Modules (SPI)263.7.8 Programmable Real-Time Unit (PRU)273.7.9 Enhanced Capture/Auxiliary PWM Modules (eCAP0)313.7.10 Enhanced Pulse Width Modulators (eHRPWM)323.7.11 Boot333.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)343.7.13 Inter-Integrated Circuit Modules(I2C0, I2C1)353.7.14 Timers363.7.15 Multichannel Audio Serial Ports (McASP)373.7.16 Multichannel Buffered Serial Ports (McBSP)383.7.17 Universal Serial Bus Modules (USB0, USB1)393.7.18 Ethernet Media Access Controller (EMAC)403.7.19 Multimedia Card/Secure Digital (MMC/SD)423.7.20 Liquid Crystal Display Controller(LCD)433.7.21 Serial ATA Controller (SATA)443.7.22 Universal Host-Port Interface (UHPI)453.7.23 Universal Parallel Port (uPP)473.7.24 Video Port Interface (VPIF)493.7.25 General Purpose Input Output513.7.26 Reserved and No Connect563.7.27 Supply and Ground573.8 Unused Pin Configurations584 Device Configuration604.1 Boot Modes604.2 SYSCFG Module604.3 Pullup/Pulldown Resistors635 Specifications645.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)645.2 Handling Ratings645.3 Recommended Operating Conditions655.4 Notes on Recommended Power-On Hours (POH)675.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)686 Peripheral Information and Electrical Specifications696.1 Parameter Information696.1.1 Parameter Information Device-Specific Information696.1.1.1 Signal Transition Levels696.2 Recommended Clock and Control Signal Transition Behavior706.3 Power Supplies706.3.1 Power-On Sequence706.3.2 Power-Off Sequence706.4 Reset716.4.1 Power-On Reset (POR)716.4.2 Warm Reset716.4.3 Reset Electrical Data Timings736.5 Crystal Oscillator or External Clock Input756.6 Clock PLLs766.6.1 PLL Device-Specific Information776.6.2 Device Clock Generation796.6.3 Dynamic Voltage and Frequency Scaling (DVFS)796.7 Interrupts816.7.1 ARM CPU Interrupts816.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy816.7.1.2 AINTC Hardware Vector Generation816.7.1.3 AINTC Hardware Interrupt Nesting Support816.7.1.4 AINTC System Interrupt Assignments826.7.1.5 AINTC Memory Map856.8 Power and Sleep Controller (PSC)876.8.1 Power Domain and Module Topology89Module States916.9 EDMA926.9.1 EDMA3 Channel Synchronization Events926.9.2 EDMA Peripheral Register Descriptions936.10 External Memory Interface A (EMIFA)986.10.1 EMIFA Asynchronous Memory Support986.10.2 EMIFA Synchronous DRAM Memory Support986.10.3 EMIFA SDRAM Loading Limitations996.10.4 External Memory Interface Register Descriptions1006.10.5 EMIFA Electrical Data/Timing1016.11 DDR2/mDDR Memory Controller1096.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing1096.11.2 DDR2/mDDR Controller Register Description(s)1106.11.3 DDR2/mDDR Interface1106.11.3.1 DDR2/mDDR Interface Schematic1106.11.3.2 Compatible JEDEC DDR2/mDDR Devices1136.11.3.3 PCB Stackup1136.11.3.4 Placement1146.11.3.5 DDR2/mDDR Keep Out Region1156.11.3.6 Bulk Bypass Capacitors1166.11.3.7 High-Speed Bypass Capacitors1166.11.3.8 Net Classes1176.11.3.9 DDR2/mDDR Signal Termination1176.11.3.10 VREF Routing1186.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing1196.11.3.12 MDDR/DDR2 Boundary Scan Limitations1216.12 Memory Protection Units1226.13 MMC / SD / SDIO (MMCSD0, MMCSD1)1256.13.1 MMCSD Peripheral Description1256.13.2 MMCSD Peripheral Register Description(s)1256.13.3 MMC/SD Electrical Data/Timing1266.14 Serial ATA Controller (SATA)1286.14.1 SATA Register Descriptions1296.14.2 SATA Interface1306.14.2.1 SATA Interface Schematic130Compatible SATA Components and Modes1306.14.2.2 PCB Stackup Specifications1316.14.2.3 Routing Specifications1316.14.2.4 Coupling Capacitors1316.14.2.5 SATA Interface Clock Source requirements1326.14.3 SATA Unused Signal Configuration1326.15 Multichannel Audio Serial Port (McASP)1336.15.1 McASP Peripheral Registers Description(s)1346.15.2 McASP Electrical Data/Timing1376.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing1376.16 Multichannel Buffered Serial Port (McBSP)1426.16.1 McBSP Peripheral Register Description(s)1426.16.2 McBSP Electrical Data/Timing1436.16.2.1 Multichannel Buffered Serial Port (McBSP) Timing1436.17 Serial Peripheral Interface Ports (SPI0, SPI1)1516.17.1 SPI Peripheral Registers Description(s)1536.17.2 SPI Electrical Data/Timing1546.17.2.1 Serial Peripheral Interface (SPI) Timing1546.18 Inter-Integrated Circuit Serial Ports (I2C)1726.18.1 I2C Device-Specific Information1726.18.2 I2C Peripheral Registers Description(s)1736.18.3 I2C Electrical Data/Timing1746.18.3.1 Inter-Integrated Circuit (I2C) Timing1746.19 Universal Asynchronous Receiver/Transmitter (UART)1766.19.1 UART Peripheral Registers Description(s)1766.19.2 UART Electrical Data/Timing1776.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]178USB Peripheral Registers Description(s)1786.20.1 USB0 [USB2.0] Electrical Data/Timing1846.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]1856.22 Ethernet Media Access Controller (EMAC)1866.22.1 EMAC Peripheral Register Description(s)1866.22.2 EMAC Electrical Data/Timing1906.23 Management Data Input/Output (MDIO)1936.23.1 MDIO Registers1936.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing1946.24 LCD Controller (LCDC)1956.24.1 LCD Interface Display Driver (LIDD Mode)1966.24.2 LCD Raster Mode2046.25 Host-Port Interface (UHPI)2106.25.1 HPI Device-Specific Information2106.25.2 HPI Peripheral Register Description(s)2106.25.3 HPI Electrical Data/Timing2116.26 Universal Parallel Port (uPP)2186.26.1 uPP Register Descriptions2196.26.2 uPP Electrical Data/Timing2206.27 Video Port Interface (VPIF)2236.27.1 VPIF Register Descriptions2236.27.2 VPIF Electrical Data/Timing2266.28 Enhanced Capture (eCAP) Peripheral2286.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)2316.29.1 eHRPWM Register Descriptions2326.29.2 Enhanced Pulse Width Modulator (eHRPWM) Timing2346.29.3 Trip-Zone Input Timing2356.30 Timers2366.30.1 Timer Electrical Data/Timing2376.31 Real Time Clock (RTC)2386.31.1 Clock Source2396.31.2 Real-Time Clock Register Descriptions2406.32 General-Purpose Input/Output (GPIO)2416.32.1 GPIO Register Description(s)2426.32.2 GPIO Peripheral Input/Output Electrical Data/Timing2446.32.3 GPIO Peripheral External Interrupts Electrical Data/Timing2446.33 Programmable Real-Time Unit Subsystem (PRUSS)2456.33.1 PRUSS Register Descriptions2466.34 Emulation Logic2486.34.1 JTAG Port Description2496.34.2 Scan Chain Configuration Parameters2506.34.3 Initial Scan Chain Configuration2506.34.3.1 Adding TAPS to the Scan Chain2506.34.4 IEEE 1149.1 JTAG2546.34.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)2546.34.4.2 JTAG Test-Port Electrical Data/Timing2556.34.5 JTAG 1149.1 Boundary Scan Considerations2557 Device and Documentation Support2567.1 Device Support2567.1.1 Development Support2567.1.2 Device and Development-Support Tool Nomenclature2567.2 Documentation Support2577.3 Community Resources2577.4 Trademarks2577.5 Electrostatic Discharge Caution2587.6 Glossary2588 Mechanical Packaging and Orderable Information2588.1 Thermal Data for ZCE Package2588.2 Thermal Data for ZWT Package259Größe: 1,87 MBSeiten: 264Language: EnglishHandbuch öffnen