Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 17: Program Status Register (PSR)
Note:
This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
different functions:
■ Application Program Status Register (APSR), bits 31:27, bits 19:16
■ Execution Program Status Register (EPSR), bits 26:24, 15:10
■ Interrupt Program Status Register (IPSR), bits 7:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (
IT
) instruction or
the Interruptible-Continuable Instruction (
ICI
) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the
MSR
instruction
always return zero. Attempts to write the EPSR using the
MSR
instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 130).
the operation that faulted (see “Exception Entry and Return” on page 130).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the
using the register name as an argument to the
MSR
or
MRS
instructions. For example, all of the
registers can be read using PSR with the
MRS
instruction, or APSR only can be written to using
APSR with the
MSR
instruction. page 101 shows the possible register combinations for the PSR. See
the
MRS
and
MSR
instruction descriptions in the Cortex™-M4 instruction set chapter in the ARM®
Cortex™-M4 Devices Generic User Guide (literature number
) for more information
about how to access the program status registers.
Table 2-3. PSR Register Combinations
Combination
Type
Register
APSR, EPSR, and IPSR
RW
a, b
PSR
EPSR and IPSR
RO
IEPSR
APSR and IPSR
RW
a
IAPSR
APSR and EPSR
RW
b
EAPSR
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type RW, reset 0x0100.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
GE
reserved
THUMB
ICI / IT
Q
V
C
Z
N
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ISRNUM
reserved
ICI / IT
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
101
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller