Benutzerhandbuch für Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X

Texas Instruments

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DK-TM4C129X

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Benutzerhandbuch (DK-TM4C129X)

Benutzerhandbuch (DK-TM4C129X)

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40
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English

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Datenbogen (DK-TM4C129X)

Inhaltsverzeichnis

Tiva™ TM4C129XNCZAD Microcontroller
1
Table of Contents
3
- List of Figures
  14
- List of Tables
  20
- List of Registers
  28
Revision History
53
About This Document
54
- Audience
  54
- About This Manual
  54
- Related Documents
  54
- Documentation Conventions
  55
1. Architectural Overview
57
- 1.1. Tiva™ C Series Overview
  57
- 1.2. TM4C129XNCZAD Microcontroller Overview
  58
- 1.3. TM4C129XNCZAD Microcontroller Features
  61
- 1.4. TM4C129XNCZAD Microcontroller Hardware Details
  87
- 1.5. Kits
  87
- 1.6. Support Information
  88
2. The Cortex-M4F Processor
89
- 2.1. Block Diagram
  90
- 2.2. Overview
  91
- 2.3. Programming Model
  93
- 2.4. Memory Model
  112
- 2.5. Exception Model
  122
  - 2.5.1. Exception States
    123
  - 2.5.2. Exception Types
    123
  - 2.5.3. Exception Handlers
    128
  - 2.5.4. Vector Table
    128
  - 2.5.5. Exception Priorities
    129
  - 2.5.6. Interrupt Priority Grouping
    130
  - 2.5.7. Exception Entry and Return
    130
    - 2.5.7.1. Exception Entry
      131
    - 2.5.7.2. Exception Return
      132
- 2.6. Fault Handling
  133
- 2.7. Power Management
  136
  - 2.7.1. Entering Sleep Modes
    136
    - 2.7.1.1. Wait for Interrupt
      136
    - 2.7.1.2. Wait for Event
      136
    - 2.7.1.3. Sleep-on-Exit
      136
  - 2.7.2. Wake Up from Sleep Mode
    136
    - 2.7.2.1. Wake Up from WFI or Sleep-on-Exit
      137
    - 2.7.2.2. Wake Up from WFE
      137
- 2.8. Instruction Set Summary
  137
3. Cortex-M4 Peripherals
144
- 3.1. Functional Description
  144
- 3.2. Register Map
  156
- 3.3. System Timer (SysTick) Register Descriptions
  159
- 3.4. NVIC Register Descriptions
  163
- 3.5. System Control Block (SCB) Register Descriptions
  173
- 3.6. Memory Protection Unit (MPU) Register Descriptions
  202
- 3.7. Floating-Point Unit (FPU) Register Descriptions
  211
4. JTAG Interface
217
- 4.1. Block Diagram
  218
- 4.2. Signal Description
  218
- 4.3. Functional Description
  219
- 4.4. Initialization and Configuration
  225
- 4.5. Register Descriptions
  225
  - 4.5.1. Instruction Register (IR)
    226
  - 4.5.2. Data Registers
    227
5. System Control
230
- 5.1. Signal Description
  230
- 5.2. Functional Description
  230
  - 5.2.1. Device Identification
    231
  - 5.2.2. Reset Control
    231
  - 5.2.3. Non-Maskable Interrupt
    238
    - 5.2.3.1. NMI Pin
      238
    - 5.2.3.2. Main Oscillator Verification Failure
      239
  - 5.2.4. Power Control
    239
  - 5.2.5. Clock Control
    240
    - 5.2.5.1. Fundamental Clock Sources
      240
    - 5.2.5.2. Clock Configuration
      242
      - Peripheral Clock Sources
        244
        ADC Clock Control
        244
        USB Clock Control
        244
        Ethernet Clock Control
        244
        PHY Interface Clocking
        244
        MII Interface Clocking
        245
        RMII Interface Clocking
        245
        PWM Clock Control
        246
        Other Peripheral Clock Control
        246
      - Optional Clock Output Signal (DIVSCLK)
        246
      - System Clock Frequency
        246
    - 5.2.5.3. Precision Internal Oscillator Operation (PIOSC)
      246
    - 5.2.5.4. Main Oscillator (MOSC)
      247
      - Main Oscillator Verification Circuit
        247
    - 5.2.5.5. PLL
      247
      - PLL Configuration
        248
      - PLL Operation
        249
  - 5.2.6. System Control
    250
    - 5.2.6.1. Run Mode
      250
    - 5.2.6.2. Sleep Mode
      250
    - 5.2.6.3. Deep-Sleep Mode
      251
    - 5.2.6.4. Dynamic Power Management
      252
      - Peripheral Power Control
        253
      - Peripheral Memory Power Control
        254
      - LDO Power Control
        254
      - Flash Memory and SRAM Power Control
        255
    - 5.2.6.5. Hibernation Mode
      255
    - 5.2.6.6. Hardware System Service Request
      255
- 5.3. Initialization and Configuration
  256
- 5.4. Register Map
  258
- 5.5. System Control Register Descriptions (System Control Offset)
  265
- 5.6. Cryptographic System Control Register Description (CCM Offset)
  551
  - Register 196: Cryptographic Modules Clock Gating Request (CCMCGREQ), offset 0x204
    552
6. Processor Support and Exception Module
553
- 6.1. Functional Description
  553
- 6.2. Register Map
  553
- 6.3. Register Descriptions
  553
7. Hibernation Module
561
- 7.1. Block Diagram
  563
- 7.2. Signal Description
  563
- 7.3. Functional Description
  564
  - 7.3.1. Register Access Timing
    565
  - 7.3.2. Hibernation Clock Source
    565
    - 7.3.2.1. Hibernate Clock Output RTCOSC
      568
  - 7.3.3. System Implementation
    568
  - 7.3.4. Battery Management
    569
  - 7.3.5. Real-Time Clock
    569
  - 7.3.6. Tamper
    572
    - 7.3.6.1. Tamper Block Diagram
      572
    - 7.3.6.2. Functional Description
      573
      - Tamper Detection
        573
      - Tamper Event Responses
        573
      - Tamper Event Logging
        574
      - Clearing a Tamper Event
        574
      - Tamper I/O Control
        575
      - Tamper Clocking
        575
      - Tamper Resets
        575
  - 7.3.7. Battery-Backed Memory
    575
  - 7.3.8. Power Control Using HIB
    575
  - 7.3.9. Power Control Using VDD3ON Mode
    576
  - 7.3.10. Initiating Hibernate
    576
  - 7.3.11. Waking from Hibernate
    576
  - 7.3.12. Arbitrary Power Removal
    577
  - 7.3.13. Interrupts and Status
    578
- 7.4. Initialization and Configuration
  578
- 7.5. Register Map
  581
- 7.6. Register Descriptions
  583
8. Internal Memory
630
- 8.1. Block Diagram
  630
- 8.2. Functional Description
  632
- 8.3. Register Map
  651
- 8.4. Internal Memory Register Descriptions (Internal Memory Control Offset)
  653
- 8.5. EEPROM Register Descriptions (EEPROM Offset)
  679
- 8.6. Memory Register Descriptions (System Control Offset)
  696
9. Micro Direct Memory Access (μDMA)
707
- 9.1. Block Diagram
  708
- 9.2. Functional Description
  708
  - 9.2.1. Channel Assignments
    709
  - 9.2.2. Priority
    710
  - 9.2.3. Arbitration Size
    711
  - 9.2.4. Request Types
    711
    - 9.2.4.1. Single Request
      712
    - 9.2.4.2. Burst Request
      712
  - 9.2.5. Channel Configuration
    712
  - 9.2.6. Transfer Modes
    714
    - 9.2.6.1. Stop Mode
      714
    - 9.2.6.2. Basic Mode
      714
    - 9.2.6.3. Auto Mode
      714
    - 9.2.6.4. Ping-Pong
      714
    - 9.2.6.5. Memory Scatter-Gather
      716
    - 9.2.6.6. Peripheral Scatter-Gather
      719
  - 9.2.7. Transfer Size and Increment
    722
  - 9.2.8. Peripheral Interface
    722
    - 9.2.8.1. FIFO Peripherals
      722
    - 9.2.8.2. Trigger Peripherals
      722
  - 9.2.9. Software Request
    723
  - 9.2.10. Interrupts and Errors
    723
- 9.3. Initialization and Configuration
  723
- 9.4. Register Map
  730
- 9.5. μDMA Channel Control Structure
  731
- 9.6. μDMA Register Descriptions
  738
10. General-Purpose Input/Outputs (GPIOs)
771
- 10.1. Signal Description
  772
- 10.2. Pad Capabilities
  777
- 10.3. Functional Description
  777
  - 10.3.1. Data Control
    779
    - 10.3.1.1. Data Direction Operation
      780
    - 10.3.1.2. Data Register Operation
      780
  - 10.3.2. Interrupt Control
    781
  - 10.3.3. Mode Control
    782
  - 10.3.4. Commit Control
    783
  - 10.3.5. Pad Control
    783
    - 10.3.5.1. Extended Drive Enable
      783
  - 10.3.6. Identification
    784
- 10.4. Initialization and Configuration
  784
- 10.5. Register Map
  786
- 10.6. Register Descriptions
  789
11. External Peripheral Interface (EPI)
846
- 11.1. EPI Block Diagram
  847
- 11.2. Signal Description
  848
- 11.3. Functional Description
  849
  - 11.3.1. Master Access to EPI
    850
  - 11.3.2. Non-Blocking Reads
    850
  - 11.3.3. DMA Operation
    851
- 11.4. Initialization and Configuration
  852
  - 11.4.1. EPI Interface Options
    853
  - 11.4.2. SDRAM Mode
    853
  - 11.4.3. Host Bus Mode
    857
  - 11.4.4. General-Purpose Mode
    878
    - 11.4.4.1. Bus Operation
      881
      - FRAME Signal Operation
        882
      - EPI Clock Operation
        884
- 11.5. Register Map
  885
- 11.6. Register Descriptions
  887
12. Cyclical Redundancy Check (CRC)
977
- 12.1. Functional Description
  977
  - 12.1.1. CRC Support
    977
    - 12.1.1.1. CRC Checksum engine
      977
    - 12.1.1.2. Data Size
      978
    - 12.1.1.3. Endian Configuration
      978
- 12.2. Initialization and Configuration
  979
  - 12.2.1. CRC Initialization and Configuration
    979
    - 12.2.1.1. Data Endian Convention for the CRC Engine
      979
- 12.3. Register Map
  980
- 12.4. CRC Module Register Descriptions
  980
13. Advance Encryption Standard Accelerator (AES)
986
- 13.1. AES Overview
  986
- 13.2. AES Functional Description
  986
  - 13.2.1. AES Block Diagram
    987
    - 13.2.1.1. Interfaces
      988
    - 13.2.1.2. Register Interface
      988
    - 13.2.1.3. AES Wide-Bus Engine
      988
      - AES Key Scheduler
        989
      - AES Encryption Core
        989
      - AES Decryption Core
        989
      - AES Feedback Mode Block
        989
      - GHASH Block
        989
  - 13.2.2. AES Algorithm
    990
  - 13.2.3. AES Operating Modes
    991
    - 13.2.3.1. Supported Modes of Operation
      991
      - ECB Feedback Mode
        991
      - CBC Feedback Mode
        991
      - CTR and ICM Feedback Modes
        992
      - CFB Mode
        993
      - F8 Mode
        993
      - XTS Operation
        994
      - F9 Operation
        995
      - CBC-MAC Operation
        995
      - GCM Operation
        996
      - CCM Operation
        997
    - 13.2.3.2. Extended and Combined Modes of Operations
      998
      - GCM Protocol Operation
        998
      - CCM Protocol Operation
        998
  - 13.2.4. AES Software Reset
    999
  - 13.2.5. Power Management
    999
  - 13.2.6. Hardware Requests
    999
- 13.3. AES Performance Information
  1000
- 13.4. AES Module Programming Guide
  1002
  - 13.4.1. AES Low - Level Programming Models
    1002
- 13.5. Register Map
  1007
- 13.6. AES Register Descriptions
  1009
- 13.7. AES µDMA Interrupt Register Descriptions (CCM Offset)
  1031
14. Data Encryption Standard Accelerator (DES)
1038
- 14.1. DES Functional Description
  1038
- 14.2. DES Block Diagram
  1039
  - 14.2.1. µDMA Control
    1039
  - 14.2.2. Interrupt Control
    1040
  - 14.2.3. Register Interface
    1040
  - 14.2.4. DES Engine
    1040
    - 14.2.4.1. Mode Control FSM
      1040
    - 14.2.4.2. DES Feedback Mode Block
      1040
    - 14.2.4.3. DES Cipher Core
      1041
- 14.3. Software Reset
  1041
- 14.4. DES Supported Modes of Operation
  1041
  - 14.4.1. ECB Feedback Mode
    1041
    - 14.4.1.1. CBC Feedback Mode
      1042
    - 14.4.1.2. CFB Feedback Mode
      1042
- 14.5. DES Module Programming Guide -Low Level Programming Models
  1043
- 14.6. Register Map
  1047
- 14.7. DES Register Description
  1048
- 14.8. DES µDMA Interrupt Register Descriptions (CCM Offset)
  1062
15. SHA/MD5 Accelerator
1067
- 15.1. SHA/MD5 Functional Description
  1067
  - 15.1.1. SHA/MD5 Block Diagram
    1067
    - 15.1.1.1. Configuration Registers
      1068
    - 15.1.1.2. Hash/HMAC Engine
      1068
    - 15.1.1.3. Hash Core Control
      1068
    - 15.1.1.4. Host Interface Bank
      1069
  - 15.1.2. Power Management
    1069
  - 15.1.3. Reset Management
    1069
  - 15.1.4. µDMA and Interrupt Requests
    1069
  - 15.1.5. Operation Description
    1070
    - 15.1.5.1. SHA Mode
      1070
      - Starting a New Hash
        1070
        Outer Digest Registers
        1072
        Inner Digest Registers
        1073
      - Closing a Hash
        1073
    - 15.1.5.2. MD5 Mode
      1075
      - Starting a New Hash
        1075
      - Closing a Hash
        1076
    - 15.1.5.3. Generating an Software Interrupt
      1076
  - 15.1.6. SHA/MD5 Performance Information
    1076
  - 15.1.7. SHA/MD5 Programming Guide
    1077
    - 15.1.7.1. Global Initialization
      1077
- 15.2. SHA/MD5 Register Map
  1081
- 15.3. SHA/MD5 Register Descriptions
  1083
- 15.4. SHA/MD5 µDMA Control Register Descriptions (Encryption Control Offset)
  1097
16. General-Purpose Timers
1102
- 16.1. Block Diagram
  1103
- 16.2. Signal Description
  1104
- 16.3. Functional Description
  1105
  - 16.3.1. GPTM Reset Conditions
    1106
  - 16.3.2. Timer Clock Source
    1106
  - 16.3.3. Timer Modes
    1107
    - 16.3.3.1. One-Shot/Periodic Timer Mode
      1107
      - Timer Compare Action Mode
        1109
    - 16.3.3.2. Real-Time Clock Timer Mode
      1109
    - 16.3.3.3. Input Edge-Count Mode
      1110
    - 16.3.3.4. Input Edge-Time Mode
      1111
    - 16.3.3.5. PWM Mode
      1113
  - 16.3.4. Wait-for-Trigger Mode
    1116
  - 16.3.5. Synchronizing GP Timer Blocks
    1117
  - 16.3.6. DMA Operation
    1118
  - 16.3.7. ADC Operation
    1118
  - 16.3.8. Accessing Concatenated 16/32-Bit GPTM Register Values
    1118
- 16.4. Initialization and Configuration
  1119
  - 16.4.1. One-Shot/Periodic Timer Mode
    1119
  - 16.4.2. Real-Time Clock (RTC) Mode
    1120
  - 16.4.3. Input Edge-Count Mode
    1120
  - 16.4.4. Input Edge Time Mode
    1121
  - 16.4.5. PWM Mode
    1121
- 16.5. Register Map
  1122
- 16.6. Register Descriptions
  1123
17. Watchdog Timers
1175
- 17.1. Block Diagram
  1176
- 17.2. Functional Description
  1176
  - 17.2.1. Register Access Timing
    1177
- 17.3. Initialization and Configuration
  1177
- 17.4. Register Map
  1177
- 17.5. Register Descriptions
  1178
18. Analog-to-Digital Converter (ADC)
1200
- 18.1. Block Diagram
  1201
- 18.2. Signal Description
  1202
- 18.3. Functional Description
  1203
  - 18.3.1. Sample Sequencers
    1204
  - 18.3.2. Module Control
    1204
    - 18.3.2.1. Interrupts
      1205
    - 18.3.2.2. DMA Operation
      1205
    - 18.3.2.3. Prioritization
      1205
    - 18.3.2.4. Sampling Events
      1205
    - 18.3.2.5. Sample and Hold Window Control
      1206
    - 18.3.2.6. Sample Phase Control
      1207
    - 18.3.2.7. Module Clocking
      1209
    - 18.3.2.8. Busy Status
      1209
    - 18.3.2.9. Dither Enable
      1210
  - 18.3.3. Hardware Sample Averaging Circuit
    1210
  - 18.3.4. Analog-to-Digital Converter
    1210
    - 18.3.4.1. Voltage Reference
      1211
  - 18.3.5. Differential Sampling
    1213
  - 18.3.6. Internal Temperature Sensor
    1215
  - 18.3.7. Digital Comparator Unit
    1216
    - 18.3.7.1. Output Functions
      1216
      - Interrupts
        1217
      - Triggers
        1217
    - 18.3.7.2. Operational Modes
      1217
      - Always Mode
        1217
      - Once Mode
        1217
      - Hysteresis-Always Mode
        1217
      - Hysteresis-Once Mode
        1218
    - 18.3.7.3. Function Ranges
      1218
      - Low-Band Operation
        1218
      - Mid-Band Operation
        1219
      - High-Band Operation
        1219
- 18.4. Initialization and Configuration
  1220
  - 18.4.1. Module Initialization
    1220
  - 18.4.2. Sample Sequencer Configuration
    1221
- 18.5. Register Map
  1221
- 18.6. Register Descriptions
  1224
19. Universal Asynchronous Receivers/Transmitters (UARTs)
1309
- 19.1. Block Diagram
  1310
- 19.2. Signal Description
  1310
- 19.3. Functional Description
  1312
  - 19.3.1. Transmit/Receive Logic
    1313
  - 19.3.2. Baud-Rate Generation
    1313
  - 19.3.3. Data Transmission
    1314
  - 19.3.4. Serial IR (SIR)
    1314
  - 19.3.5. ISO 7816 Support
    1316
  - 19.3.6. Modem Handshake Support
    1316
    - 19.3.6.1. Signaling
      1316
    - 19.3.6.2. Flow Control
      1317
      - Hardware Flow Control (RTS/CTS)
        1317
      - Software Flow Control (Modem Status Interrupts)
        1317
  - 19.3.7. 9-Bit UART Mode
    1317
  - 19.3.8. FIFO Operation
    1318
  - 19.3.9. Interrupts
    1318
  - 19.3.10. Loopback Operation
    1319
  - 19.3.11. DMA Operation
    1319
- 19.4. Initialization and Configuration
  1320
- 19.5. Register Map
  1321
- 19.6. Register Descriptions
  1323
20. Quad Synchronous Serial Interface (QSSI)
1375
- 20.1. Block Diagram
  1375
- 20.2. Signal Description
  1376
- 20.3. Functional Description
  1378
- 20.4. Initialization and Configuration
  1389
  - 20.4.1. Enhanced Mode Configuration
    1391
- 20.5. Register Map
  1391
- 20.6. Register Descriptions
  1392
21. Inter-Integrated Circuit (I2C) Interface
1424
- 21.1. Block Diagram
  1425
- 21.2. Signal Description
  1426
- 21.3. Functional Description
  1427
  - 21.3.1. I2C Bus Functional Overview
    1427
    - 21.3.1.1. START and STOP Conditions
      1428
    - 21.3.1.2. Data Format with 7-Bit Address
      1428
    - 21.3.1.3. Data Validity
      1429
    - 21.3.1.4. Acknowledge
      1429
    - 21.3.1.5. Repeated Start
      1430
    - 21.3.1.6. Clock Low Timeout (CLTO)
      1430
    - 21.3.1.7. Dual Address
      1431
    - 21.3.1.8. Arbitration
      1431
    - 21.3.1.9. Glitch Suppression in Multi-Master Configuration
      1432
    - 21.3.1.10. SMBus Operation
      1432
      - Quick Command
        1432
  - 21.3.2. Available Speed Modes
    1433
    - 21.3.2.1. Standard, Fast, and Fast Plus Modes
      1433
    - 21.3.2.2. High-Speed Mode
      1434
  - 21.3.3. Interrupts
    1435
  - 21.3.4. Loopback Operation
    1436
  - 21.3.5. FIFO and µDMA Operation
    1436
    - 21.3.5.1. Master Module Burst Mode
      1437
      - Master Module µDMA Functionality
        1437
    - 21.3.5.2. Slave Module
      1438
  - 21.3.6. Command Sequence Flow Charts
    1438
    - 21.3.6.1. I2C Master Command Sequences
      1438
    - 21.3.6.2. I2C Slave Command Sequences
      1446
- 21.4. Initialization and Configuration
  1446
  - 21.4.1. Configure the I2C Module to Transmit a Single Byte as a Master
    1446
  - 21.4.2. Configure the I2C Master to High Speed Mode
    1447
- 21.5. Register Map
  1448
- 21.6. Register Descriptions (I2C Master)
  1450
- 21.7. Register Descriptions (I2C Slave)
  1479
- 21.8. Register Descriptions (I2C Status and Control)
  1496
22. 1-Wire Master Module
1505
- 22.1. Block Diagram
  1505
- 22.2. Signal Description
  1506
- 22.3. Functional Description
  1506
  - 22.3.1. 1-Wire Protocol
    1506
  - 22.3.2. Transport Protocol
    1509
  - 22.3.3. Overdrive
    1510
  - 22.3.4. Timing Override
    1510
  - 22.3.5. Command Protocol
    1511
  - 22.3.6. Search (Enumeration) and Sub-Byte
    1512
  - 22.3.7. Interrupts
    1512
  - 22.3.8. DMA
    1512
  - 22.3.9. 1-Wire Timing
    1514
- 22.4. Initialization and Configuration
  1514
- 22.5. Register Map
  1515
- 22.6. 1-Wire Master Register Descriptions
  1516
23. Controller Area Network (CAN) Module
1534
- 23.1. Block Diagram
  1535
- 23.2. Signal Description
  1535
- 23.3. Functional Description
  1536
- 23.4. Register Map
  1553
- 23.5. CAN Register Descriptions
  1554
24. Ethernet Controller
1585
- 24.1. Block Diagram
  1586
- 24.2. Signal Description
  1586
- 24.3. Functional Description
  1588
  - 24.3.1. Ethernet Clock Control
    1588
    - 24.3.1.1. PHY Interface
      1588
    - 24.3.1.2. MII Interface
      1589
    - 24.3.1.3. RMII Interface
      1590
  - 24.3.2. MII/RMII Interface Signals
    1591
  - 24.3.3. DMA Controller
    1592
    - 24.3.3.1. Burst Access
      1593
    - 24.3.3.2. Data Buffer Alignment
      1594
    - 24.3.3.3. Buffer Size Calculations
      1594
    - 24.3.3.4. DMA Arbiter
      1595
    - 24.3.3.5. DMA Transmission Operation
      1595
      - TX DMA Default Operation
        1595
      - TX DMA OSF Mode Operation
        1598
      - Transmit Frame Processing
        1599
      - Transmit Polling Suspended
        1600
    - 24.3.3.6. DMA Receive Operation
      1600
      - Default Receive Operation
        1600
      - Receive Descriptor Acquisition
        1602
      - Receive Frame Processing
        1603
      - Receive Process Suspend
        1603
    - 24.3.3.7. DMA Interrupts
      1603
    - 24.3.3.8. DMA Bus Error
      1605
  - 24.3.4. Descriptors
    1605
    - 24.3.4.1. Transmit Descriptor
      1605
    - 24.3.4.2. Receive Descriptor
      1609
    - 24.3.4.3. IEEE 1588-2005 Timestamp Descriptor Format
      1612
    - 24.3.4.4. Enhanced Descriptors
      1613
      - Enhanced Transmit Descriptor
        1613
      - Enhanced Receive Descriptor
        1618
  - 24.3.5. TX/RX Controller
    1624
    - 24.3.5.1. Transmit (TX) Control Path
      1624
      - Transmit Operation
        1625
      - Collision and Retransmission
        1625
      - TX FIFO Flush Operation
        1626
      - Transmit Status Word
        1626
    - 24.3.5.2. Receive (RX) Control Path
      1626
      - Receive Operation
        1626
      - Error Handling
        1627
      - Receive Word Status
        1627
    - 24.3.5.3. MAC Flow Control
      1628
  - 24.3.6. MAC Operation
    1628
  - 24.3.7. IEEE 1588 and Advanced Timestamp Function
    1631
    - 24.3.7.1. System Time Module
      1632
    - 24.3.7.2. Transmit Timestamping
      1634
    - 24.3.7.3. Receive Timestamping
      1635
    - 24.3.7.4. Timestamp Error Margin
      1635
    - 24.3.7.5. IEEE 1588-2008 Advanced Timestamps
      1635
      - Peer-to-Peer Transparent Clock Message Support
        1636
      - Advanced Timestamp Supported Clock Types
        1637
      - PTP Processing and Control
        1637
      - Reference Timing Source
        1637
        80-Bit Timestamp
        1637
        Fixed Pulse-Per-Second Output
        1638
        Flexible Pulse-Per-Second Output
        1638
      - Advanced Timestamp Transmit Path Functions
        1639
      - Advanced Timestamp Receive Path Functions
        1639
  - 24.3.8. Frame Filtering
    1639
    - 24.3.8.1. VLAN Filtering
      1639
  - 24.3.9. Source Address, VLAN, and CRC Insertion, Replacement or Deletion
    1640
  - 24.3.10. Checksum Offload Engine
    1642
    - 24.3.10.1. Transmit Checksum Offload Engine
      1642
    - 24.3.10.2. IP Header Checksum Engine
      1642
  - 24.3.11. MAC Management Counters
    1643
  - 24.3.12. Power Management Module
    1643
    - 24.3.12.1. Remote Wake-Up
      1644
      - Filter n Byte Mask
        1644
      - Filter n Command
        1644
      - Filter n Offset
        1644
      - Filter n CRC-16
        1645
    - 24.3.12.2. Remote Wake-Up Frame Detection
      1645
    - 24.3.12.3. Magic Packet Detection
      1645
    - 24.3.12.4. Power Management Interrupts
      1646
    - 24.3.12.5. Power-Down/Wake-Up Sequence
      1646
  - 24.3.13. Serial Management Interface
    1646
  - 24.3.14. Reduced Media Independent Interface (RMII)
    1647
  - 24.3.15. Interrupt Configuration
    1647
- 24.4. EMAC Initialization and Configuration
  1647
- 24.5. Ethernet PHY
  1648
  - 24.5.1. Integrated PHY Block Diagram
    1649
  - 24.5.2. Functional Description
    1649
    - 24.5.2.1. Auto-Negotiation
      1649
    - 24.5.2.2. Auto-MDIX
      1650
    - 24.5.2.3. Isolate Mode
      1650
    - 24.5.2.4. LED Interface
      1650
    - 24.5.2.5. PHY Address
      1651
    - 24.5.2.6. Serial Management Interface
      1651
    - 24.5.2.7. Extended Address Space Access
      1651
      - Write to PHY Registers
        1652
      - Write to Extended PHY Registers
        1652
      - Read from PHY Registers
        1654
      - Read from Extended PHY Registers
        1654
  - 24.5.3. Initialization and Configuration
    1655
    - 24.5.3.1. Interface Configuration
      1655
    - 24.5.3.2. Functional Configuration and Initialization
      1656
- 24.6. Register Map
  1657
- 24.7. Ethernet MAC Register Descriptions
  1661
- 24.8. Ethernet PHY Register Descriptions
  1783
25. Universal Serial Bus (USB) Controller
1838
- 25.1. Block Diagram
  1839
- 25.2. Signal Description
  1839
- 25.3. Register Map
  1840
26. LCD Controller
1847
- 26.1. Block Diagram
  1847
- 26.2. Signal Description
  1848
- 26.3. Functional Description
  1850
  - 26.3.1. LCD DMA Engine
    1850
    - 26.3.1.1. Interrupts
      1851
      - LIDD Mode
        1851
      - Raster Mode
        1851
  - 26.3.2. LIDD Bus Operation
    1852
  - 26.3.3. Raster Control
    1853
    - 26.3.3.1. Logical Data Path
      1854
  - 26.3.4. Clocking
    1856
  - 26.3.5. LCD Frame Buffer
    1857
  - 26.3.6. Palette
    1863
  - 26.3.7. Gray-Scaler/Serializer - Passive (STN) Mode
    1863
  - 26.3.8. Gray-Scaler/Serializer - Active (TFT) Mode
    1863
  - 26.3.9. Color/Grayscale Intensities and Modulation Rates
    1863
  - 26.3.10. Summary of Color Depth
    1864
  - 26.3.11. Output Format
    1864
    - 26.3.11.1. Passive (STN) Mode
      1864
    - 26.3.11.2. Active (TFT) Mode
      1864
  - 26.3.12. Subpicture Feature
    1865
- 26.4. Interrupts
  1866
- 26.5. Bus Transaction Modes
  1867
- 26.6. Initialization and Configuration
  1867
- 26.7. Register Map
  1868
- 26.8. Register Descriptions
  1869
27. Analog Comparators
1915
- 27.1. Block Diagram
  1916
- 27.2. Signal Description
  1916
- 27.3. Functional Description
  1917
  - 27.3.1. Internal Reference Programming
    1918
- 27.4. Initialization and Configuration
  1920
- 27.5. Register Map
  1921
- 27.6. Register Descriptions
  1921
28. Pulse Width Modulator (PWM)
1931
- 28.1. Block Diagram
  1932
- 28.2. Signal Description
  1934
- 28.3. Functional Description
  1934
  - 28.3.1. Clock Configuration
    1934
  - 28.3.2. PWM Timer
    1935
  - 28.3.3. PWM Comparators
    1935
  - 28.3.4. PWM Signal Generator
    1936
  - 28.3.5. Dead-Band Generator
    1937
  - 28.3.6. Interrupt/ADC-Trigger Selector
    1937
  - 28.3.7. Synchronization Methods
    1938
  - 28.3.8. Fault Conditions
    1939
  - 28.3.9. Output Control Block
    1940
- 28.4. Initialization and Configuration
  1940
- 28.5. Register Map
  1941
- 28.6. Register Descriptions
  1944
29. Quadrature Encoder Interface (QEI)
2010
- 29.1. Block Diagram
  2010
- 29.2. Signal Description
  2012
- 29.3. Functional Description
  2012
- 29.4. Initialization and Configuration
  2015
- 29.5. Register Map
  2015
- 29.6. Register Descriptions
  2016
30. Pin Diagram
2033
31. Signal Tables
2034
- 31.1. Signals by Pin Number
  2035
- 31.2. Signals by Signal Name
  2054
- 31.3. Signals by Function, Except for GPIO
  2070
- 31.4. GPIO Pins and Alternate Functions
  2087
- 31.5. Possible Pin Assignments for Alternate Functions
  2092
- 31.6. Connections for Unused Signals
  2099
32. Electrical Characteristics
2101
- 32.1. Maximum Ratings
  2101
- 32.2. Operating Characteristics
  2102
- 32.3. Recommended Operating Conditions
  2103
  - 32.3.1. DC Operating Conditions
    2103
  - 32.3.2. Recommended GPIO Operating Characteristics
    2103
    - 32.3.2.1. GPIO Current Restrictions
      2104
      - I/O Reliability
        2105
- 32.4. Load Conditions
  2105
- 32.5. JTAG and Boundary Scan
  2106
- 32.6. Power and Brown-Out
  2107
  - 32.6.1. VDDA Levels
    2108
  - 32.6.2. VDD Levels
    2109
  - 32.6.3. VDDC Levels
    2110
  - 32.6.4. Response
    2111
    - 32.6.4.1. VDD Glitch Response
      2111
    - 32.6.4.2. VDD Droop Response
      2111
- 32.7. Reset
  2112
- 32.8. On-Chip Low Drop-Out (LDO) Regulator
  2114
- 32.9. Clocks
  2115
  - 32.9.1. PLL Specifications
    2115
    - 32.9.1.1. PLL Configuration
      2115
  - 32.9.2. PIOSC Specifications
    2117
  - 32.9.3. Low-Frequency Internal Oscillator Specifications
    2117
  - 32.9.4. Hibernation Clock Source Specifications
    2117
  - 32.9.5. Main Oscillator Specifications
    2119
  - 32.9.6. System Clock Specification with ADC Operation
    2122
  - 32.9.7. System Clock Specification with USB Operation
    2122
- 32.10. Sleep Modes
  2122
- 32.11. Hibernation Module
  2123
- 32.12. Flash Memory
  2124
- 32.13. EEPROM
  2125
- 32.14. Input/Output Pin Characteristics
  2126
  - 32.14.1. Types of I/O Pins and ESD Protection
    2128
    - 32.14.1.1. Hibernate WAKE pin
      2128
    - 32.14.1.2. Non-Power I/O Pins
      2128
- 32.15. External Peripheral Interface (EPI)
  2129
- 32.16. Analog-to-Digital Converter (ADC)
  2136
- 32.17. Synchronous Serial Interface (SSI)
  2142
- 32.18. Inter-Integrated Circuit (I2C) Interface
  2145
- 32.19. Ethernet Controller
  2146
  - 32.19.1. DC Characteristics
    2146
  - 32.19.2. Clock Characteristics
    2146
  - 32.19.3. AC Characteristics
    2148
- 32.20. Universal Serial Bus (USB) Controller
  2154
- 32.21. LCD Controller
  2155
  - 32.21.1. LCD Interface Display Driver (LIDD Mode)
    2156
    - 32.21.1.1. Hitachi Mode
      2157
    - 32.21.1.2. Motorola 6800 Mode
      2160
    - 32.21.1.3. Intel 8080 Mode
      2162
  - 32.21.2. LCD Raster Mode
    2165
- 32.22. Analog Comparator
  2171
- 32.23. Current Consumption
  2173
Appendix A. Package Information
2176
- A.1. Orderable Devices
  2176
- A.2. Part Markings
  2177
- A.3. Packaging Diagram
  2178
- A.4. Packaging Materials
  2179

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