Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 25: AES Data RW Plaintext/Ciphertext 0 (AES_DATA_IN_0), offset
0x060
0x060
Register 26: AES Data RW Plaintext/Ciphertext 1 (AES_DATA_IN_1), offset
0x064
0x064
Register 27: AES Data RW Plaintext/Ciphertext 2 (AES_DATA_IN_2), offset
0x068
0x068
Register 28: AES Data RW Plaintext/Ciphertext 3 (AES_DATA_IN_3), offset
0x06C
0x06C
The AES Data RW Plaintext/Ciphertext n (AES_DATA_IN_n) registers are used to read and write
plaintext/ciphertext. The AES_DATA_IN_0 register contains the most significant word; the
AES_DATA_IN_3 register contains least significant word.
plaintext/ciphertext. The AES_DATA_IN_0 register contains the most significant word; the
AES_DATA_IN_3 register contains least significant word.
Note:
The AES_DATA_IN_0 register acts as a FIFO and shifts data into the other
AES_DATA_IN_n registers.
AES_DATA_IN_n registers.
AES Data RW Plaintext/Ciphertext (AES_DATA_IN_n)
Base 0x4403.6000
Offset 0x060
Type RW, reset 0x0000.0000
Offset 0x060
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DATA
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DATA
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Secure Data RW Plaintext/Ciphertext
This field holds the plaintext/ciphertext data.
0x00000000
RW
DATA
31:0
December 13, 2013
1020
Texas Instruments-Advance Information
Advance Encryption Standard Accelerator (AES)