Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode, and indicates whether the FPU state is active. This register is only
accessible in privileged mode.
the processor is in Thread mode, and indicates whether the FPU state is active. This register is only
accessible in privileged mode.
Handler mode always uses the MSP, so the processor ignores explicit writes to the
ASP
bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 133).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses the MSP. To
switch the stack pointer used in Thread mode to the PSP, either use the
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 133).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses the MSP. To
switch the stack pointer used in Thread mode to the PSP, either use the
MSR
instruction to set the
ASP
bit, as detailed in the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number
), or perform an exception return to Thread
mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 133.
Note:
When changing the stack pointer, software must use an
ISB
instruction immediately after
the
MSR
instruction, ensuring that instructions after the
ISB
execute use the new stack
pointer. See the Cortex™-M4 instruction set chapter in the ARM® Cortex™-M4 Devices
Generic User Guide (literature number
Generic User Guide (literature number
).
Control Register (CONTROL)
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TMPL
ASP
FPCA
reserved
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
31:3
Floating-Point Context Active
Description
Value
Floating-point context active
1
No floating-point context active
0
The Cortex-M4F uses this bit to determine whether to preserve
floating-point state when processing an exception.
floating-point state when processing an exception.
Important:
Two bits control when
FPCA
can be enabled: the
ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the
register and the
DISFPCA
bit in the Auxiliary Control
(ACTLR) register.
0
RW
FPCA
2
December 13, 2013
108
Texas Instruments-Advance Information
The Cortex-M4F Processor