Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 9: GPTM Interrupt Clear (GPTMICR), offset 0x024
This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.
GPTM Interrupt Clear (GPTMICR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x024
Type W1C, reset 0x0000.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x024
Type W1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TATOCINT
CAMCINT
CAECINT
RTCCINT
TAMCINT
DMAAINT
reserved
TBTOCINT
CBMCINT
CBECINT
TBMCINT
reserved
DMABINT
reserved
W1C
W1C
W1C
W1C
W1C
W1C
RO
RO
W1C
W1C
W1C
W1C
RO
W1C
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000
RO
reserved
31:14
GPTM Timer B DMA Done Interrupt Clear
Writing a 1 to this bit clears the
DMABRIS
bit in the GPTMRIS register
and the
DMABMIS
bit in the GPTMMIS register.
0
W1C
DMABINT
13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
12
GPTM Timer B Match Interrupt Clear
Writing a 1 to this bit clears the
TBMRIS
bit in the GPTMRIS register
and the
TBMMIS
bit in the GPTMMIS register.
0
W1C
TBMCINT
11
GPTM Timer B Capture Mode Event Interrupt Clear
Writing a 1 to this bit clears the
CBERIS
bit in the GPTMRIS register
and the
CBEMIS
bit in the GPTMMIS register.
0
W1C
CBECINT
10
GPTM Timer B Capture Mode Match Interrupt Clear
Writing a 1 to this bit clears the
CBMRIS
bit in the GPTMRIS register
and the
CBMMIS
bit in the GPTMMIS register.
0
W1C
CBMCINT
9
GPTM Timer B Time-Out Interrupt Clear
Writing a 1 to this bit clears the
TBTORIS
bit in the GPTMRIS register
and the
TBTOMIS
bit in the GPTMMIS register.
0
W1C
TBTOCINT
8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
7:6
1149
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller