Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 31: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064
Register 32: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
These registers contain the configuration information for each sample for a sequence executed with
Sample Sequencer 1 or 2. When configuring a sample sequence, the
Sample Sequencer 1 or 2. When configuring a sample sequence, the
END
bit must be set for the
final sample, whether it be after the first sample, fourth sample, or any sample in between. These
registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0
register on page 1259 for detailed bit descriptions. The ADCSSCTL1 register configures Sample
Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2.
registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0
register on page 1259 for detailed bit descriptions. The ADCSSCTL1 register configures Sample
Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2.
ADC Sample Sequence Control n (ADCSSCTLn)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x064
Type RW, reset 0x0000.0000
ADC1 base: 0x4003.9000
Offset 0x064
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D0
END0
IE0
TS0
D1
END1
IE1
TS1
D2
END2
IE2
TS2
D3
END3
IE3
TS3
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000
RO
reserved
31:16
4th Sample Temp Sensor Select
Description
Value
The input pin specified by the ADCSSMUXn register is read
during the fourth sample of the sample sequence.
during the fourth sample of the sample sequence.
0
The temperature sensor is read during the fourth sample of the
sample sequence.
sample sequence.
1
0
RW
TS3
15
4th Sample Interrupt Enable
Description
Value
The raw interrupt is not asserted to the interrupt controller.
0
The raw interrupt signal (
INR0
bit) is asserted at the end of the
fourth sample's conversion. If the
MASK0
bit in the ADCIM
register is set, the interrupt is promoted to the interrupt controller.
1
It is legal to have multiple samples within a sequence generate interrupts.
0
RW
IE3
14
December 13, 2013
1278
Texas Instruments-Advance Information
Analog-to-Digital Converter (ADC)