Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 5: Ethernet MAC MII Address (EMACMIIADDR), offset 0x010
The Ethernet MAC MII address (EMACMIIADDR) register controls the management cycles to the
PHY through the management interface.
PHY through the management interface.
Ethernet MAC MII Address (EMACMIIADDR)
Base 0x400E.C000
Offset 0x010
Type RW, reset 0x0000.0000
Offset 0x010
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MIIB
MIIW
CR
MII
PLA
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
31:16
Physical Layer Address
This field gives the PHY address of the MII module. Values 1- 31 (0x1
to 0x1F) are available for external PHY addresses.
to 0x1F) are available for external PHY addresses.
Note:
The integrated PHY's address is 0x00. To access the
integrated PHY registers, the
integrated PHY registers, the
PLA
bits[15:11] must be zeros.
0x0
RW
PLA
15:11
MII Register
These bits select the desired MII registers in the selected PHY device.
0x0
RW
MII
10:6
Clock Reference Frequency Selection
The clock that is sent to the MAC Clock and Status (CSR) registers is
the gated System Clock (SYSCLK). The SYSCLK is divided down
through the CR field to produce an MDC clock that is approximately
between the frequency range 1.0 MHz - 2.5 MHz. The application must
program the appropriate
the gated System Clock (SYSCLK). The SYSCLK is divided down
through the CR field to produce an MDC clock that is approximately
between the frequency range 1.0 MHz - 2.5 MHz. The application must
program the appropriate
CR
field based on the System Clock input.
Description
Value
The frequency of the System Clock is 60 to 100 MHz providing
a MDIO clock of SYSCLK/42.
a MDIO clock of SYSCLK/42.
0x0
The frequency of the System Clock is 100 to 150 MHz
providing a MDIO clock of SYSCLK/62.
providing a MDIO clock of SYSCLK/62.
0x1
The frequency of the System Clock is 20-35 MHz providing
a MDIO clock of System Clock/16.
a MDIO clock of System Clock/16.
0x2
The frequency of the System Clock is 35 to 60 MHz providing
a MDIO clock of System Clock/26.
a MDIO clock of System Clock/26.
0x3
reserved
0x4-0xF
0x0
RW
CR
5:2
1675
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller