Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 12: Ethernet MAC Raw Interrupt Status (EMACRIS), offset 0x038
The Ethernet MAC Raw Interrupt Status (EMACRIS) register identifies the events in the MAC
that can generate interrupt.
that can generate interrupt.
Ethernet MAC Raw Interrupt Status (EMACRIS)
Base 0x400E.C000
Offset 0x038
Type RO, reset 0x0000.0000
Offset 0x038
Type RO, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
PMT
MMC
MMCRX
MMCTX
reserved
TS
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.0
RO
reserved
31:10
Timestamp Interrupt Status
This bit is cleared by reading the
TSSOVF
bit in the MAC timestamp
Status Register (EMACTIMSTAT) register.
In this mode, this bit is cleared after the completion of the read of this
bit. In all other modes, this bit is reserved.
bit. In all other modes, this bit is reserved.
Description
Value
No timestamp interrupt is present.
0
When the advanced timestamp feature is enabled, this bit
indicates one of two conditions is true:
indicates one of two conditions is true:
1
■
The system time value equals or exceeds the value
specified in the EMAC Target Time Seconds Register
(EMACTARGSEC) and MAC Target Time Nanoseconds
(EMACTARGNANO) registers.
specified in the EMAC Target Time Seconds Register
(EMACTARGSEC) and MAC Target Time Nanoseconds
(EMACTARGNANO) registers.
■
There is an overflow in the EMAC Target Time Seconds
(EMACTARGSEC) register.
(EMACTARGSEC) register.
When default timestamping is enabled, this bit indicates that
the system time value is equal to or exceeds the value specified
in the EMAC Target Time registers. In this mode, this bit is
cleared after the completion of the read of this bit.
the system time value is equal to or exceeds the value specified
in the EMAC Target Time registers. In this mode, this bit is
cleared after the completion of the read of this bit.
0x0
RO
TS
9
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
8:7
1689
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller