Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 27: Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM),
offset 0x110
offset 0x110
The MAC MMC Transmit Interrupt Mask (EMACMMCTXIM) register maintains the masks for the
interrupts generated when the transmit statistic counters reach half of their maximum value or
maximum value. This register is 32-bits wide.
interrupts generated when the transmit statistic counters reach half of their maximum value or
maximum value. This register is 32-bits wide.
Ethernet MAC MMC Transmit Interrupt Mask (EMACMMCTXIM)
Base 0x400E.C000
Offset 0x110
Type RW, reset 0x0000.0000
Offset 0x110
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
OCTCNT
reserved
RO
RO
RO
RO
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
GBF
reserved
SCOLLGF
MCOLLGF
RO
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
31:21
MMC Transmit Good Octet Counter Interrupt Mask
Description
Value
An interrupt is sent to the interrupt controller when the
OCTCNT
bit in the EMACMMCTXRIS register is set.
0
The
OCTCNT
interrupt is suppressed and not sent to the interrupt
controller.
1
0x0
RW
OCTCNT
20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
19:16
MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
Description
Value
An interrupt is sent to the interrupt controller when the
MCOLLGF
bit in the EMACMMCTXRIS register is set.
0
The
MCOLLGF
interrupt is suppressed and not sent to the
interrupt controller.
1
0x0
RW
MCOLLGF
15
MMC Transmit Single Collision Good Frame Counter Interrupt Mask
Description
Value
An interrupt is sent to the interrupt controller when the
SCOLLGF
bit in the EMACMMCTXRIS register is set.
0
The
SCOLLGF
interrupt is suppressed and not sent to the
interrupt controller.
1
0x0
RW
SCOLLGF
14
1713
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller