Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 88: Ethernet PHY MII Interrupt Status 1 - MR18 (EPHYMISR1), address
0x012
0x012
This register contains events status and enables for the interrupt function. If an event has occurred
since the last read of this register, the corresponding status bit is set. If the corresponding enable
bit in the register is set, an interrupt is generated if the event occurs. The
since the last read of this register, the corresponding status bit is set. If the corresponding enable
bit in the register is set, an interrupt is generated if the event occurs. The
INTEN
bit (Bit 1) in the
EPHYSCR register (0x011) must also be set to allow interrupts. The status indications in this register
are set even if the interrupt is not enabled.
are set even if the interrupt is not enabled.
Ethernet PHY MII Interrupt Status 1 - MR18 (EPHYMISR1)
Base n/a
Address 0x012
Type RW, reset 0x0000
Address 0x012
Type RW, reset 0x0000
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RXHFEN
FCHFEN
ANCEN
DUPLEXMEN
SPEEDEN
LINKSTATEN
reserved
RXHF
FCHF
ANC
DUPLEXM
SPEED
LINKSTAT
reserved
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
15:14
Change of Link Status Interrupt
Reading this bit clears the interrupt and thus, the status bit.
Description
Value
No change of link status.
0
Change of link status interrupt is pending.
1
0
RO
LINKSTAT
13
Change of Speed Status Interrupt
Reading this bit clears the interrupt and thus, the status bit.
Description
Value
No change of speed status.
0
Change of speed status interrupt is pending.
1
0
RO
SPEED
12
Change of Duplex Status Interrupt
Reading this bit clears the interrupt and thus, the status bit.
Description
Value
No change of duplex status.
0
Duplex status change interrupt is pending.
1
0
RO
DUPLEXM
11
Auto-Negotiation Complete Interrupt
Reading this bit clears the interrupt and thus, the status bit.
Description
Value
No Auto-negotiation complete event is pending.
0
Auto-negotiation complete interrupt is pending.
1
0
RO
ANC
10
December 13, 2013
1816
Texas Instruments-Advance Information
Ethernet Controller