Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Figure 26-7. 24 bpp Color RGB Remapping on LCDDATA[23:0]
0
23
23
B[7:0]
0
24 bit pixel data
retrieved from
DDR
24 bit remapped
LCD pixel data
bus output
15
G[7:0]
R[7:0]
R[0] G[0]
B[0] R[1] G[1] B[1]
B[2]
R[2]
R[7:3]
G[7:2]
B[7:3]
8 7
15
16
22
21
20
19
18
17
16
11 10
5
Data format for 16 bpp
The LCD controller is configured to support 16 bpp raw data format when
TFT24
= 0x0,
LCDTFT
=
0x1,
TFTMAP
= 0x0 in the LCDRASTRCTL register. Two 16 bpp raw data pixels can be stored in
one word in DDR. The configuration is shown in Figure 26-8 on page 1861. For color component
ordering, pixel data is in a RGB565 configuration and is output on the LCD pixel data bus LCDDATA[
15:0] in the same order. LCDDATA bits [23:16] are undefined in 16 bpp mode. Figure 26-9 on page 1861
shows the configuration of the pixel data retrieved from memory and LCD bus output.
ordering, pixel data is in a RGB565 configuration and is output on the LCD pixel data bus LCDDATA[
15:0] in the same order. LCDDATA bits [23:16] are undefined in 16 bpp mode. Figure 26-9 on page 1861
shows the configuration of the pixel data retrieved from memory and LCD bus output.
Figure 26-8. 16 bpp Data Format
Pixel 1 [15:0]
Pixel 0 [15:0]
Pixel 3 [15:0]
Word X
Word X + 1
Word X + 2
0
31
16 15
0
31
16 15
0
31
16 15
Pixel 2 [15:0]
Pixel 4 [15:0]
Pixel 5 [15:0]
Figure 26-9. 16 bpp Color Component Ordering
0
23
11
B[4:0]
0
16-bit pixel data
retrieved from
DDR
16 bpp color data
bus output
(LCDDATA[23:0])
15
G[5:0]
R[4:0]
B[4:0]
G[5:0]
R[4:0]
5 4
15
10
16
11 10
5 4
Unused
Data Format for 12 bpp
Two pixel data are stored in each 32-bit word in memory. The upper four bits in each 16-bit halfword
are unused. Figure 26-10 on page 1862 shows the 12bpp data format.
are unused. Figure 26-10 on page 1862 shows the 12bpp data format.
1861
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller