Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Palette Loading Delay
This 8-bit parameter pauses reading of the Palette data from the
asynchronous FIFO between each burst of 16 words. The delay is in
terms of system clock (SYSCLK) cycles. The value (0-255) used to
specify the number of system clock cycles that should be paused
between bursts of 16 word reads from the asynchronous FIFO while
loading the Palette SRAM. Programming
asynchronous FIFO between each burst of 16 words. The delay is in
terms of system clock (SYSCLK) cycles. The value (0-255) used to
specify the number of system clock cycles that should be paused
between bursts of 16 word reads from the asynchronous FIFO while
loading the Palette SRAM. Programming
REQDLY
=0x00 disables this
pause when loading the Palette table.
When loading the Palette from system memory, palette data is burst
into the internal Palette SRAM from the Asynchronous FIFO. 1, 2, and
4-bit per pixel frame buffer encodings use a fixed 16-word entry palette
residing above the video data.
into the internal Palette SRAM from the Asynchronous FIFO. 1, 2, and
4-bit per pixel frame buffer encodings use a fixed 16-word entry palette
residing above the video data.
The 8-bit per pixel frame buffer encoding uses a 256-word entry palette
residing above the video data. Likewise, 12, 16, and 24-bit per pixel
frame buffer encodings also define a 256-word entry palette even though
these encodings will not do a full bit-depth palette lookup. However, the
256-word palette entry must still be read from DDR as a frame buffer is
fetched.
residing above the video data. Likewise, 12, 16, and 24-bit per pixel
frame buffer encodings also define a 256-word entry palette even though
these encodings will not do a full bit-depth palette lookup. However, the
256-word palette entry must still be read from DDR as a frame buffer is
fetched.
Bursting in 256 words in sequential SYSCLK cycles may cause the
asynchronous FIFO to underflow depending on the DDR burst
bandwidth.
asynchronous FIFO to underflow depending on the DDR burst
bandwidth.
0x00
RW
REQDLY
19:12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
11:10
Mono 8-Bit
This bit is ignored in all other modes.
Description
Value
lcd_pixel_o[3:0] is used to output four pixel values to the panel
each pixel clock transition
each pixel clock transition
0
lcd_pixel_o[7:0] is used to output eight pixel values to the panel
each pixel clock transition.
each pixel clock transition.
1
0
RW
MONO8B
9
Raster Data Order Select
For 1, 2, 4, and 8 BPP framebuffers.
This bit has no effect on raw data framebuffers (12/16/24 bpp). This bit
is used to determine palette indexing and is used in conjunction with
is used to determine palette indexing and is used in conjunction with
NIBMODE
.
Description
Value
The framebuffer parsing for Palette Data lookup is from Bit 0 to
bit 31 of the input word from the DMA output.
bit 31 of the input word from the DMA output.
0
The famebuffer parsing for Palette Data lookup is from Bit 31
to Bit 0 of the input word from the DMA output.
to Bit 0 of the input word from the DMA output.
1
0
RW
RDORDER
8
December 13, 2013
1884
Texas Instruments-Advance Information
LCD Controller