Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 14: LCD Raster Subpanel Display 1 (LCDRASTRSUBP1), offset 0x038
Note that subpictures are only allowed for Active Matrix mode (
LCDTFT
=1) in LCDRASTRCTL
LCD Raster Subpanel Display 1 (LCDRASTRSUBP1)
Base 0x4405.0000
Offset 0x038
Type RW, reset 0x0000.0000
Offset 0x038
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LPPT
reserved
HOLS
reserved
SPEN
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RW
RO
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DPDLSB
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Sub Panel Enable
Description
Value
Function disabled
0
Sub-panel function mode enabled
1
0
RW
SPEN
31
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
30
High or Low Signal
This field indicates the position of the sub-panel based on the
LPPT
value.
Description
Value
Default Pixel Data lines are at the top of the screen and the
active video lines are at the bottom of the screen.
active video lines are at the bottom of the screen.
0
Active video lines are at the top of the screen and Default Pixel
Data lines are at the bottom of the screen.
Data lines are at the bottom of the screen.
1
0
RW
HOLS
29
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
28:26
Line Per Panel Threshold
Encoded value (programmed value range of {0:2047} represents an
actual range of {1:2048}) used to specify the number of lines on the
bottom part of the panel. Bit 10 of this field is in LCDRASTRSUBP2.
actual range of {1:2048}) used to specify the number of lines on the
bottom part of the panel. Bit 10 of this field is in LCDRASTRSUBP2.
HOLS
determines whether Default Pixel Data is on the top (
HOLS
=0) or
on the bottom (
HOLS
=1).
LPPT
defines the number of lines on the bottom
part of the output.
0x000
RW
LPPT
25:16
Default Pixel Data LSB[15:0]
DPD defines the default value of the pixel data sent to the panel for the
lines until
lines until
LPPT
is reach or after passing
LPPT
.
DPDMSB
is defined in
bit field [7:0] in LCDRASTRSUBP2.
0x0000
RW
DPDLSB
15:0
1891
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller