Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000
This register provides a summary of the interrupt status (masked) of the comparators.
Analog Comparator Masked Interrupt Status (ACMIS)
Base 0x4003.C000
Offset 0x000
Type RW1C, reset 0x0000.0000
Offset 0x000
Type RW1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IN0
IN1
IN2
reserved
RW1C
RW1C
RW1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
31:3
Comparator 2 Masked Interrupt Status
Description
Value
No interrupt has occurred or the interrupt is masked.
0
The
IN2
bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
IN2
bit
in the ACRIS register.
0
RW1C
IN2
2
Comparator 1 Masked Interrupt Status
Description
Value
No interrupt has occurred or the interrupt is masked.
0
The
IN1
bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
IN1
bit
in the ACRIS register.
0
RW1C
IN1
1
Comparator 0 Masked Interrupt Status
Description
Value
No interrupt has occurred or the interrupt is masked.
0
The
IN0
bits in the ACRIS register and the ACINTEN registers
are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
IN0
bit
in the ACRIS register.
0
RW1C
IN0
0
December 13, 2013
1922
Texas Instruments-Advance Information
Analog Comparators