Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 76: MPU Region Attribute and Size (MPUATTR), offset 0xDA0
Register 77: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
Register 78: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
Register 79: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
Note:
This register can only be accessed from privileged mode.
The MPUATTR register defines the region size and memory attributes of the MPU region specified
by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions.
by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant
halfword holding the region attributes and the least-significant halfword holds the region size and
the region and subregion enable bits.
halfword holding the region attributes and the least-significant halfword holds the region size and
the region and subregion enable bits.
The MPU access permission attribute bits,
XN
,
AP
,
TEX
,
S
,
C
, and
B
, control access to the
corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
permissions, then the MPU generates a permission fault.
The
SIZE
field defines the size of the MPU memory region specified by the MPUNUMBER register
as follows:
(Region size in bytes) = 2
(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a
SIZE
value of 4. Table
3-10 on page 209 gives example
SIZE
values with the corresponding region size and value of N in
the MPU Region Base Address (MPUBASE) register.
Table 3-10. Example SIZE Field Values
Note
Value of N
a
Region Size
SIZE
Encoding
Minimum permitted size
5
32 B
00100b (0x4)
-
10
1 KB
01001b (0x9)
-
20
1 MB
10011b (0x13)
-
30
1 GB
11101b (0x1D)
Maximum possible size
No valid
ADDR
field in MPUBASE; the
region occupies the complete
memory map.
memory map.
4 GB
11111b (0x1F)
a. Refers to the N parameter in the MPUBASE register (see page 207).
MPU Region Attribute and Size (MPUATTR)
Base 0xE000.E000
Offset 0xDA0
Type RW, reset 0x0000.0000
Offset 0xDA0
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
B
C
S
TEX
reserved
AP
reserved
XN
reserved
RW
RW
RW
RW
RW
RW
RO
RO
RW
RW
RW
RO
RW
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ENABLE
SIZE
reserved
SRD
RW
RW
RW
RW
RW
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
209
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller