Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 14: Deep Sleep Clock Configuration Register (DSCLKCFG), offset
0x144
0x144
The DSCLKCFG register specifies the behavior of the clock system while in deep sleep.
Note that the
MOSCDPD
bit not only affects deep-sleep mode, but all other modes as well depending
on the value of the bit. Please refer to the following table when programming this bit:
Table 5-13. MOSC Configurations
Result
MOSCDPD
field
PWRDN
bit
MOSC is powered ON in run and sleep modes, but is disabled in accidental power down,
when the
when the
PWRDN
bit is set in the MOSCCTL register, or in deep-sleep mode only if it is not
the deep-sleep clock source (
DSOSCSRC
!==0x3).
0
0
MOSC is powered and running in run, sleep and deep-sleep modes.
1
0
MOSC is powered off, and does not run in any mode. Please note, that in this configuration,
when the MOSC is disabled, the MOSC must not be chosen as a clock source or indeterminate
results occur.
when the MOSC is disabled, the MOSC must not be chosen as a clock source or indeterminate
results occur.
0
1
MOSC runs and does not disable itself in run, sleep, and deep-sleep modes regardless of
the fact that the
the fact that the
PWRDN
bit is set.
1
1
Note:
The MOSCDPD bit has an effect in all modes of operation
Note:
If the MOSC is chosen as the Deep-Sleep clock source in the DSCLKCFG register, the
MOSC must also be configured as the Run and Sleep clock source in the RSCLKCFG
register prior to entering Deep Sleep. If the PIOSC, LFIOSC, or Hibernation RTC Module
Oscillator (HIBLFIOSC or 32-kHz crystal) is configured as the Run and Sleep clock source
in the RSCLKFCFG register, and the MOSC is configured as the Deep-Sleep clock source
in the DSCLKCFG register, then two outcomes are possible:
MOSC must also be configured as the Run and Sleep clock source in the RSCLKCFG
register prior to entering Deep Sleep. If the PIOSC, LFIOSC, or Hibernation RTC Module
Oscillator (HIBLFIOSC or 32-kHz crystal) is configured as the Run and Sleep clock source
in the RSCLKFCFG register, and the MOSC is configured as the Deep-Sleep clock source
in the DSCLKCFG register, then two outcomes are possible:
■ If the PIOSC is still powered in Deep Sleep (using the
PIOSCPD
bit in the DSCLKCFG
register) then the PIOSC is utilized as the clock source when entering Deep Sleep and
the device enters and exits the Deep-Sleep state normally. The MOSC is not used as
the clock source in Deep Sleep.
the device enters and exits the Deep-Sleep state normally. The MOSC is not used as
the clock source in Deep Sleep.
■ If the PIOSC has been configured to be powered down in Deep Sleep, then the device
can enter the Deep-Sleep state, but cannot exit properly. This situation can be avoided
by programming the MOSC as the Run and Sleep clock source in the RSCLKCFG
register prior to entering Deep Sleep.
by programming the MOSC as the Run and Sleep clock source in the RSCLKCFG
register prior to entering Deep Sleep.
Deep Sleep Clock Configuration Register (DSCLKCFG)
Base 0x400F.E000
Offset 0x144
Type RW, reset 0x0000.0000
Offset 0x144
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
DSOSCSRC
reserved
MOSCDPD
PIOSCPD
RO
RO
RO
RO
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DSSYSDIV
reserved
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
December 13, 2013
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