Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen

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DK-TM4C129X

2.4.5

Bit-Banding ................................................................................................................. 118

2.4.6

Data Storage .............................................................................................................. 120

2.4.7

Synchronization Primitives ........................................................................................... 121

2.5

Exception Model ......................................................................................................... 122

2.5.1

Exception States ......................................................................................................... 123

2.5.2

Exception Types .......................................................................................................... 123

2.5.3

Exception Handlers ..................................................................................................... 128

2.5.4

Vector Table ................................................................................................................ 128

2.5.5

Exception Priorities ...................................................................................................... 129

2.5.6

Interrupt Priority Grouping ............................................................................................ 130

2.5.7

Exception Entry and Return ......................................................................................... 130

2.6

Fault Handling ............................................................................................................. 133

2.6.1

Fault Types ................................................................................................................. 134

2.6.2

Fault Escalation and Hard Faults .................................................................................. 134

2.6.3

Fault Status Registers and Fault Address Registers ...................................................... 135

2.6.4

Lockup ....................................................................................................................... 135

2.7

Power Management .................................................................................................... 136

2.7.1

Entering Sleep Modes ................................................................................................. 136

2.7.2

Wake Up from Sleep Mode .......................................................................................... 136

2.8

Instruction Set Summary .............................................................................................. 137

Cortex-M4 Peripherals ......................................................................................... 144

3.1

Functional Description ................................................................................................. 144

3.1.1

System Timer (SysTick) ............................................................................................... 145

3.1.2

Nested Vectored Interrupt Controller (NVIC) .................................................................. 146

3.1.3

System Control Block (SCB) ........................................................................................ 147

3.1.4

Memory Protection Unit (MPU) ..................................................................................... 147

3.1.5

Floating-Point Unit (FPU) ............................................................................................. 152

3.2

Register Map .............................................................................................................. 156

3.3

System Timer (SysTick) Register Descriptions .............................................................. 159

3.4

NVIC Register Descriptions .......................................................................................... 163

3.5

System Control Block (SCB) Register Descriptions ........................................................ 173

3.6

Memory Protection Unit (MPU) Register Descriptions .................................................... 202

3.7

Floating-Point Unit (FPU) Register Descriptions ............................................................ 211

JTAG Interface ...................................................................................................... 217

4.1

Block Diagram ............................................................................................................ 218

4.2

Signal Description ....................................................................................................... 218

4.3

Functional Description ................................................................................................. 219

4.3.1

JTAG Interface Pins ..................................................................................................... 219

4.3.2

JTAG TAP Controller ................................................................................................... 221

4.3.3

Shift Registers ............................................................................................................ 222

4.3.4

Operational Considerations .......................................................................................... 222

4.4

Initialization and Configuration ..................................................................................... 225

4.5

Register Descriptions .................................................................................................. 225

4.5.1

Instruction Register (IR) ............................................................................................... 226

4.5.2

Data Registers ............................................................................................................ 227

System Control ..................................................................................................... 230

5.1

Signal Description ....................................................................................................... 230

5.2

Functional Description ................................................................................................. 230

December 13, 2013

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