Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 4: System Exception Interrupt Clear (SYSEXCIC), offset 0x00C
The SYSEXCIC register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
System Exception Interrupt Clear (SYSEXCIC)
Base 0x400F.9000
Offset 0x00C
Type W1C, reset 0x0000.0000
Offset 0x00C
Type W1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FPIDCIC
FPDZCIC
FPIOCIC
FPUFCIC
FPOFCIC
FPIXCIC
reserved
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
W1C
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.00
W1C
reserved
31:6
Floating-Point Inexact Exception Interrupt Clear
Writing a 1 to this bit clears the
FPIXCRIS
bit in the SYSEXCRIS register
and the
FPIXCMIS
bit in the SYSEXCMIS register.
0
W1C
FPIXCIC
5
Floating-Point Overflow Exception Interrupt Clear
Writing a 1 to this bit clears the
FPOFCRIS
bit in the SYSEXCRIS register
and the
FPOFCMIS
bit in the SYSEXCMIS register.
0
W1C
FPOFCIC
4
Floating-Point Underflow Exception Interrupt Clear
Writing a 1 to this bit clears the
FPUFCRIS
bit in the SYSEXCRIS register
and the
FPUFCMIS
bit in the SYSEXCMIS register.
0
W1C
FPUFCIC
3
Floating-Point Invalid Operation Interrupt Clear
Writing a 1 to this bit clears the
FPIOCRIS
bit in the SYSEXCRIS register
and the
FPIOCMIS
bit in the SYSEXCMIS register.
0
W1C
FPIOCIC
2
Floating-Point Divide By 0 Exception Interrupt Clear
Writing a 1 to this bit clears the
FPDZCRIS
bit in the SYSEXCRIS register
and the
FPDZCMIS
bit in the SYSEXCMIS register.
0
W1C
FPDZCIC
1
Floating-Point Input Denormal Exception Interrupt Clear
Writing a 1 to this bit clears the
FPIDCRIS
bit in the SYSEXCRIS register
and the
FPIDCMIS
bit in the SYSEXCMIS register.
0
W1C
FPIDCIC
0
December 13, 2013
560
Texas Instruments-Advance Information
Processor Support and Exception Module