Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 22: HIB Tamper Status (HIBTPSTAT), offset 0x404
The HIB Tamper Status (HIBTPCTL) register provides status of the module.
Note:
Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the
WRC
bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the
WRC
bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 565. The HIBIO register and bits
RSTWK
,
PADIOWK
and
WC
of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the
CLK32EN
bit in the HIBCTL
register has been set may produce unexpected results.
Note:
Errant writes to the Tamper registers are protected by the Hibernate HIBLOCK register.
HIB Tamper Status (HIBTPSTAT)
Base 0x400F.C000
Offset 0x404
Type RW1C, reset 0x0000.0000
Offset 0x404
Type RW1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XOSCFAIL
XOSCST
STATE
reserved
RW1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31:4
Tamper Module Status
Tamper is defined as being configured when the tamper I/Os have been
enabled (setting the
enabled (setting the
ENx
bits in the HIBTPIO register).
Description
Value
Tamper disabled.
0x0
Tamper configured.
0x1
Tamper pin event occurred.
0x2
0
RO
STATE
3:2
External Oscillator Status
Description
Value
Active
0
Stopped
1
0
RO
XOSCST
1
619
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller