Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type RW1C, reset 0x0000.0000
Offset 0x014
Type RW1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AMISC
PMISC
EMISC
reserved
VOLTMISC
INVDMISC
ERMISC
reserved
PROGMISC
reserved
RW1C
RW1C
RW1C
RO
RO
RO
RO
RO
RO
RW1C
RW1C
RW1C
RO
RW1C
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
31:14
PROGVER Masked Interrupt Status and Clear
Description
Value
When read, a 0 indicates that an interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled.
signaled.
Writing a 1 to this bit clears
PROGMISC
and also the
PROGRIS
bit in the FCRIS register (see page 659).
1
0
RW1C
PROGMISC
13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
12
ERVER Masked Interrupt Status and Clear
Description
Value
When read, a 0 indicates that an interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
When read, a 1 indicates that an unmasked interrupt was
signaled.
signaled.
Writing a 1 to this bit clears
ERMISC
and also the
ERRIS
bit in
the FCRIS register (see page 659).
1
0
RW1C
ERMISC
11
December 13, 2013
664
Texas Instruments-Advance Information
Internal Memory