Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 13: Flash Configuration Register (FLASHCONF), offset 0xFC8
The FLASHCONF register allows the user to enable or disable various properties of the Flash. The
force bits,
force bits,
FBFON
and
FBFOFF
, can be used to test code performance and execution by turning the
prefetch buffers on and subsequently forcing them off.
Flash Configuration Register (FLASHCONF)
Base 0x400F.D000
Offset 0xFC8
Type RW, reset 0x0000.0000
Offset 0xFC8
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FPFOFF
FPFON
reserved
CLRTV
reserved
SPFE
FMME
reserved
RW
RW
RO
RO
RW
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RO
Type
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31
Flash Mirror Mode Enable
Description
Value
Flash mirror mode is disabled.
0
Flash mirror mode feature is enabled. Access to the lower banks
is translated to upper.
is translated to upper.
1
0x0
RW
FMME
30
Single Prefetch Mode Enable
Description
Value
A 4x256-bit prefetch buffer is enabled and used.
0
A single 2x256-bit prefetch buffer is enabled and used.
1
0x0
RW
SPFE
29
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000
RO
reserved
28:21
Clear Valid Tags
This is a self-clearing bit.
Description
Value
No effect.
0
Clear valid tags in the prefetch buffer.
1
0
RW
CLRTV
20
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
19:18
December 13, 2013
674
Texas Instruments-Advance Information
Internal Memory