Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 16: Flash DMA Starting Address (FLASHDMAST), offset 0xFD4
The starting address for the Flash region accessible by the µDMA is programmed in the
FLASHDMAST register.
FLASHDMAST register.
Note:
The µDMA can access Flash in Run Mode only (not available in low power modes).
Flash DMA Starting Address (FLASHDMAST)
Base 0x400F.D000
Offset 0xFD4
Type RW, reset 0x0000.0000
Offset 0xFD4
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ADDR
reserved
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
ADDR
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
31:29
Contains the starting address of the flash region accessible by µDMA
if the FLASHPP register
if the FLASHPP register
DFA
bit is set
0x0
RW
ADDR
28:11
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
10:0
8.5
EEPROM Register Descriptions (EEPROM Offset)
This section lists and describes the EEPROM registers, in numerical order by address offset.
Registers in this section are relative to the EEPROM base address of 0x400A.F000.
Registers in this section are relative to the EEPROM base address of 0x400A.F000.
Note that the EEPROM module clock must be enabled before the registers can be programmed
(see page 416). There must be a delay of 3 system clocks after the EEPROM module clock is enabled
before any EEPROM module registers are accessed. In addition, after enabling or resetting the
EEPROM module, software must wait until the
(see page 416). There must be a delay of 3 system clocks after the EEPROM module clock is enabled
before any EEPROM module registers are accessed. In addition, after enabling or resetting the
EEPROM module, software must wait until the
WORKING
bit in the EEDONE register is clear before
accessing any EEPROM registers.
679
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller