Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C
Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit
clears the corresponding
clears the corresponding
SET[n]
bit in the DMAENASET register.
DMA Channel Enable Clear (DMAENACLR)
Base 0x400F.F000
Offset 0x02C
Type WO, reset -
Offset 0x02C
Type WO, reset -
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CLR[n]
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Type
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLR[n]
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Type
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reset
Description
Reset
Type
Name
Bit/Field
Clear Channel [n] Enable Clear
Description
Value
No effect.
0
Setting a bit clears the corresponding
SET[n]
bit in the
DMAENASET register meaning that channel [n] is disabled for
μDMA transfers.
μDMA transfers.
1
Note:
The controller disables a channel when it completes the μDMA
cycle.
cycle.
-
WO
CLR[n]
31:0
751
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller