Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038
Each bit of the DMAPRIOSET register represents the corresponding µDMA channel. Setting a bit
configures the µDMA channel to have a high priority level. Reading the register returns the status
of the channel priority mask.
configures the µDMA channel to have a high priority level. Reading the register returns the status
of the channel priority mask.
DMA Channel Priority Set (DMAPRIOSET)
Base 0x400F.F000
Offset 0x038
Type RW, reset 0x0000.0000
Offset 0x038
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
SET[n]
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SET[n]
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Channel [n] Priority Set
Description
Value
µDMA channel [n] is using the default priority level.
0
µDMA channel [n] is using a high priority level.
1
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding
corresponding
CLR[n]
bit in the DMAPRIOCLR register.
0x0000.0000
RW
SET[n]
31:0
December 13, 2013
754
Texas Instruments-Advance Information
Micro Direct Memory Access (μDMA)