Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
used as GPIOs or for other functions. For example, when using a 4-bit address with an 8-bit
data, the pins assigned to
data, the pins assigned to
EPIS0[23:8]
can be assigned to other functions.
■ Data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by the
DSIZE
field in the EPIGPCFG
register). By default, the EPI controller uses data bits [7:0] when the
DSIZE
field in the EPIGPCFG
register is 0x0; data bits [15:0] when the
DSIZE
field is 0x1; data bits [23:0] when the
DSIZE
field is 0x2; and data bits [31:0] when the
DSIZE
field is 0x3.32-bit data cannot be used with
address or EPI clock or any other signal. 24-bit data can only be used with 4-bit address or no
address.
address.
■ When using the EPI controller as a GPIO interface, writes are FIFOed (up to 4 can be held at
any time), and up to 32 pins are changed using the EPIBAUD clock rate specified by
COUNT0
.
As a result, output pin control can be very precisely controlled as a function of time. By contrast,
when writing to normal GPIOs, writes can only occur 8-bits at a time and take up to two clock
cycles to complete. In addition, the write itself may be further delayed by the bus due to μDMA
or draining of a previous write. With both GPIO and the EPI controller, reads may be performed
directly, in which case the current pin states are read back. With the EPI controller, the
non-blocking interface may also be used to perform reads based on a fixed time rule via the
EPIBAUD clock rate.
when writing to normal GPIOs, writes can only occur 8-bits at a time and take up to two clock
cycles to complete. In addition, the write itself may be further delayed by the bus due to μDMA
or draining of a previous write. With both GPIO and the EPI controller, reads may be performed
directly, in which case the current pin states are read back. With the EPI controller, the
non-blocking interface may also be used to perform reads based on a fixed time rule via the
EPIBAUD clock rate.
Table 11-12 on page 880 shows how the
EPI0S[31:0]
signals function while in General-Purpose
mode. Notice that the address connections vary depending on the data-width restrictions of the
external peripheral.
external peripheral.
Table 11-12. EPI General-Purpose Signal Connections
General- Purpose
Signal (D32)
General- Purpose
Signal (D24, A4)
General- Purpose
Signal (D16, A12)
General-Purpose
Signal (D8, A20)
EPI Signal
D0
D0
D0
D0
EPI0S0
D1
D1
D1
D1
EPI0S1
D2
D2
D2
D2
EPI0S2
D3
D3
D3
D3
EPI0S3
D4
D4
D4
D4
EPI0S4
D5
D5
D5
D5
EPI0S5
D6
D6
D6
D6
EPI0S6
D7
D7
D7
D7
EPI0S7
D8
D8
D8
A0
EPI0S8
D9
D9
D9
A1
EPI0S9
D10
D10
D10
A2
EPI0S10
D11
D11
D11
A3
EPI0S11
D12
D12
D12
A4
EPI0S12
D13
D13
D13
A5
EPI0S13
D14
D14
D14
A6
EPI0S14
D15
D15
D15
A7
EPI0S15
D16
D16
A0
a
A8
EPI0S16
D17
D17
A1
A9
EPI0S17
D18
D18
A2
A10
EPI0S18
D19
D19
A3
A11
EPI0S19
D20
D20
A4
A12
EPI0S20
December 13, 2013
880
Texas Instruments-Advance Information
External Peripheral Interface (EPI)