Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X Datenbogen
Produktcode
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Read Stall Error
Description
Value
The Read Stalled error interrupt is disabled. Reads behave as
normal and are stalled until any preceding writes have completed
and the read has returned a result.
normal and are stalled until any preceding writes have completed
and the read has returned a result.
0
This bit enables the Read Stalled error interrupt (
RSTALL
in the
EPIEISC register) to be generated when a read is attempted
and the WFIFO is not empty. The read is still stalled during the
time the WFIFO drains, but this error notifies the application
that this excess delay has occurred.
and the WFIFO is not empty. The read is still stalled during the
time the WFIFO drains, but this error notifies the application
that this excess delay has occurred.
1
Note that the configuration of this bit has no effect on non-blocking reads.
0
RW
RSERR
16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
RO
reserved
15:7
Write FIFO
Description
Value
Interrupt is triggered while WRFIFO is empty. It will be
deasserted when not empty. This encoding is optimized for
burst of 4 writes.
deasserted when not empty. This encoding is optimized for
burst of 4 writes.
0x0
reserved
0x1
Interrupt is triggered until there are only two slots available.
Thus, trigger is deasserted when there are two WRFIFO
entries present. This configuration is optimized for bursts of
2.
Thus, trigger is deasserted when there are two WRFIFO
entries present. This configuration is optimized for bursts of
2.
0x2
Interrupt is triggered until there is one WRFIFO entry
available. This configuration expects only single writes.
available. This configuration expects only single writes.
0x3
Trigger interrupt when WRFIFO is not full, meaning trigger
will continue to assert until there are four entries in the
WRFIFO.
will continue to assert until there are four entries in the
WRFIFO.
0x4
reserved
0x5-0x7
0x3
RW
WRFIFO
6:4
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
3
Read FIFO
This field configures the trigger point for the NBRFIFO.
Description
Value
reserved
0x0
Trigger when there are 1 or more entries in the NBRFIFO.
0x1
Trigger when there are 2 or more entries in the NBRFIFO.
0x2
Trigger when there are 4 or more entries in the NBRFIFO.
0x3
Trigger when there are 6 or more entries in the NBRFIFO.
0x4
Trigger when there are 7 or more entries in the NBRFIFO.
0x5
Trigger when there are 8 entries in the NBRFIFO.
0x6
reserved
0x7
0x3
RW
RDFIFO
2:0
935
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller