Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
4.7.3
Pin Multiplexing Details
This section discusses how to program each Pin Mux Register to select the desired peripheral functions
and pin muxing. See the individual pin mux sections for pin muxing details for a specific muxed pin.
and pin muxing. See the individual pin mux sections for pin muxing details for a specific muxed pin.
For details on PINMUX0 and PINMUX1 registers, see
, Pin Muxing Selection After Reset.
4.7.3.1
PCI, HPI, EMIFA, and ATA Pin Muxing
The PCI, HPI, EMIFA, and ATA signal muxing is determined by the value of the PCIEN, HPIEN, and
ATAEN bit fields in the PINMUX0 register. For more details on the actual pin functions, see
ATAEN bit fields in the PINMUX0 register. For more details on the actual pin functions, see
and
Table 4-24. PCIEN, HPIEN, and ATAEN Encoding
PCIEN
HPIEN
ATAEN
PIN FUNCTIONS
0
0
0
EMIFA
0
0
1
EMIFA (NAND) and ATA
0
1
0
HPI (32-bit)
0
1
1
HPI (16-bit) and ATA
1
x
x
PCI
(1)
(1)
In PCI mode (PCIEN = 1), the internal pullups/pulldowns (IPUs/IPDs) are disabled on all PCI pins and
it is recommended to have external pullup resistors on the PCI_RSV[5:0] pins. See
it is recommended to have external pullup resistors on the PCI_RSV[5:0] pins. See
for the
actual PCI pin functions and any associated footnotes.
Table 4-25. PCI, HPI, EMIFA, and ATA Pin Muxing
PIN FUNCTIONS (WITH PCIEN, HPIEN, ATAEN VALUES)
1xx
(1)
010
011
000
001
PCI_CLK
GP[10]
GP[10]
GP[10]
GP[10]
PCI_IDSEL
–
HDDIR
EM_R/W
HDDIR
PCI_DEVSEL
HCNTL1
HCNTL1
EM_BA[1]
EM_BA[1]
PCI_FRAME
HINT
HINT
EM_BA[0]
EM_BA[0]
PCI_IRDY
HRDY
HRDY
EM_A[17]
EM_A[17]/(CLE)
PCI_TRDY
HHWIL
HHWIL
EM_A[16]
EM_A[16]/(ALE)
PCI_STOP
HCNTL0
HCNTL0
EM_WE
EM_WE
PCI_SERR
HDS1
HDS1
EM_OE
EM_OE
PCI_PERR
HCS
HCS
EM_DQM1
EM_DQM1
PCI_PAR
HAS
HAS
EM_DQM0
EM_DQM0
PCI_INTA
–
–
EM_WAIT2
EM_WAIT2/(RDY2/BSY2)
PCI_REQ
GP[11]
DMARQ
EM_CS5
DMARQ
PCI_GNT
GP[12]
DACK
EM_CS4
DACK
PCI_CBE3
HR/W
HR/W
EM_CS3
EM_CS3
PCI_CBE2
HDS2
HDS2
EM_CS2
EM_CS2
PCI_CBE1
GP[32]
ATA_CS1
EM_A[19]
ATA_CS1
PCI_CBE0
GP[33]
ATA_CS0
EM_A[18]
ATA_CS0
PCI_AD31
HD31
DD15
EM_A[15]
DD15
PCI_AD30
HD30
DD14
EM_A[14]
DD14
PCI_AD29
HD29
DD13
EM_A[13]
DD13
PCI_AD28
HD28
DD12
EM_A[12]
DD12
PCI_AD27
HD27
DD11
EM_A[11]
DD11
(1)
In PCI mode (PCIEN = 1), the internal pullups/pulldowns (IPUs/IPDs) are disabled on all PCI pins and it is recommended to have
external pullup resistors on the PCI_RSV[5:0] pins. For more detailed information on external pullup/pulldown resistors, see
external pullup resistors on the PCI_RSV[5:0] pins. For more detailed information on external pullup/pulldown resistors, see
, Pullup/Pulldown Resistors.
Copyright © 2009–2012, Texas Instruments Incorporated
Device Configurations
113
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