Benutzerhandbuch für Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T

Inhaltsverzeichnis

• 1 Digital Media System-on-Chip (DMSoC)

  1
  • 1.1 Features

    1
  • 1.2 Description

    3
  • 1.3 Functional Block Diagram

    5
• Table of Contents

  6
• 2 Revision History

  7
• 3 Device Overview

  8
  • 3.1 Device Characteristics

    8
  • 3.2 Device Compatibility

    10
  • 3.3 ARM Subsystem

    10
    • 3.3.1 ARM926EJ-S RISC CPU

      10
    • 3.3.2 CP15

      11
    • 3.3.3 MMU

      11
    • 3.3.4 Caches and Write Buffer

      11
    • 3.3.5 Tightly Coupled Memory (TCM)

      12
    • 3.3.6 Advanced High-Performance Bus (AHB)

      12
    • 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

      12
    • 3.3.8 ARM Memory Mapping

      12
      • 3.3.8.1 ARM Internal Memories

        12
      • 3.3.8.2 External Memories

        12
      • 3.3.8.3 DSP Memories

        13
      • 3.3.8.4 ARM-DSP Integration

        13
    • 3.3.9 Peripherals

      13
    • 3.3.10 PLL Controller (PLLC)

      13
    • 3.3.11 Power and Sleep Controller (PSC)

      13
    • 3.3.12 ARM Interrupt Controller (AINTC)

      13
    • 3.3.13 System Module

      14
    • 3.3.14 Power Management

      14
  • 3.4 DSP Subsystem

    14
    • 3.4.1 C64x+ DSP CPU Description

      14
    • 3.4.2 DSP Memory Mapping

      17
      • 3.4.2.1 ARM Internal Memories

        17
      • 3.4.2.2 External Memories

        17
      • 3.4.2.3 DSP Internal Memories

        17
      • 3.4.2.4 C64x+ CPU

        17
    • 3.4.3 Peripherals

      18
    • 3.4.4 DSP Interrupt Controller

      18
  • 3.5 Memory Map Summary

    19
  • 3.6 Pin Assignments

    23
    • 3.6.1 Pin Map (Bottom View)

      23
  • 3.7 Terminal Functions

    30
  • 3.8 Device Support

    78
    • 3.8.1 Development Support

      78
    • 3.8.2 Device and Development-Support Tool Nomenclature

      78
  • 3.9 Documentation Support

    80
    • 3.9.1 Related Documentation From Texas Instruments

      80
  • 3.10 Community Resources

    80
• 4 Device Configurations

  81
  • 4.1 System Module Registers

    81
  • 4.2 Power Considerations

    83
  • 4.3 Clock Considerations

    86
    • 4.3.1 Clock Configurations after Device Reset

      86
      • 4.3.1.1 Device Clock Frequency

        86
      • 4.3.1.2 Module Clock State

        86
    • 4.3.2 Clock Control

      88
      • 4.3.2.1 Video Clock Control Register

        88
      • 4.3.2.2 TSIF Control

        89
      • 4.3.2.3 Video and TSIF Clock Disable

        90
    • 4.3.3 Clock and Oscillator Control

      91
  • 4.4 Boot Sequence

    93
    • 4.4.1 Boot Modes

      93
    • 4.4.2 Boot Mode Registers

      93
      • 4.4.2.1 DSPBOOTADDR Register

        93
      • 4.4.2.2 BOOTSTAT Register

        94
      • 4.4.2.3 BOOTCFG Register

        95
      • 4.4.2.4 ARMBOOT Register

        97
      • 4.4.2.5 ARMWAIT Register

        97
  • 4.5 Configurations At Reset

    99
    • 4.5.1 Device and Peripheral Configurations at Device Reset

      99
    • 4.5.2 EMIFA CS2 Bus Width (CS2BW)

      100
    • 4.5.3 PCI Enable (PCIEN)

      100
    • 4.5.4 DSPBOOT

      101
  • 4.6 Configurations After Reset

    102
    • 4.6.1 Switch Central Resource (SCR) Bus Priorities

      102
    • 4.6.2 Peripheral Selection After Device Reset

      105
      • 4.6.2.1 HPICTL Register

        106
      • 4.6.2.2 USBCTL Register

        106
      • 4.6.2.3 PWMCTL (Trigger Source) Control Register

        108
      • 4.6.2.4 EDMATCCFG Register

        109
  • 4.7 Multiplexed Pin Configurations

    110
    • 4.7.1 Pin Muxing Selection At Reset

      110
    • 4.7.2 Pin Muxing Selection After Reset

      110
      • 4.7.2.1 PINMUX0 Register Description

        110
      • 4.7.2.2 PINMUX1 Register Description

        112
    • 4.7.3 Pin Multiplexing Details

      113
      • 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing

        113
      • 4.7.3.2 PWM Signal Muxing

        115
      • 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)

        116
      • 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)

        117
      • 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)

        118
      • 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)

        119
      • 4.7.3.7 CRGEN Signal Muxing

        120
      • 4.7.3.8 UART0 Pin Muxing

        121
      • 4.7.3.9 UART1 Pin Muxing

        123
      • 4.7.3.10 UART2 Pin Muxing

        124
      • 4.7.3.11 ARM/DSP Communications Interrupts

        126
      • 4.7.3.12 Emulation Control

        130
  • 4.8 Debugging Considerations

    132
    • 4.8.1 Pullup/Pulldown Resistors

      132
• 5 System Interconnect

  134
• 6 Device Operating Conditions

  135
  • 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

    135
  • 6.2 Recommended Operating Conditions

    136
  • 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)

    137
• 7 Peripheral Information and Electrical Specifications

  139
  • 7.1 Parameter Information

    139
    • 7.1.1  1.8-V and 3.3-V Signal Transition Levels

      139
    • 7.1.2  3.3-V Signal Transition Rates

      139
    • 7.1.3 Timing Parameters and Board Routing Analysis

      140
  • 7.2 Recommended Clock and Control Signal Transition Behavior

    140
  • 7.3 Power Supplies

    141
    • 7.3.1 Power-Supply Sequencing

      141
    • 7.3.2 Power-Supply Design Considerations

      141
    • 7.3.3 Power-Supply Decoupling

      141
    • 7.3.4 DM6467T Power and Clock Domains

      141
    • 7.3.5 Power and Sleep Controller (PSC)

      145
  • 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins

    149
    • 7.4.1 Clock Input Option 1—Crystal

      149
      • 7.4.1.1 33.3-MHz for System Oscillator Clock Input Option 1—Crystal

        149
      • 7.4.1.2 24-MHz Auxiliary Oscillator Clock Input Option 1—Crystal

        150
    • 7.4.2 Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input

      152
      • 7.4.2.1 33.3-MHz System Oscillator Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input

        152
      • 7.4.2.2 24-MHz Auxiliary Oscillator Clock Input Option 2—1.8-V LVCMOS-Compatible Clock Input

        152
  • 7.5 Clock PLLs

    153
    • 7.5.1 PLL1 and PLL2

      153
    • 7.5.2 PLL Controller Register Description(s)

      156
    • 7.5.3  Clock PLL Considerations With External Clock Sources

      157
    • 7.5.4 Output Clocks (CLKOUT0, AUDIO_CLK1, AUDIO_CLK0) - Clock Select Logic

      157
    • 7.5.5  Clock PLL Electrical Data/Timing (Input and Output Clocks)

      159
  • 7.6 Enhanced Direct Memory Access (EDMA3) Controller

    162
    • 7.6.1 EDMA3 Channel Synchronization Events

      162
    • 7.6.2 EDMA Peripheral Register Description(s)

      165
  • 7.7 Reset

    182
    • 7.7.1 Power-on Reset (POR Pin)

      182
      • 7.7.1.1 Usage of POR versus RESET Pins

        183
      • 7.7.1.2 Latching Boot and Configuration Pins

        183
    • 7.7.2 Warm Reset (RESET Pin)

      183
    • 7.7.3 Maximum Reset

      184
    • 7.7.4 System Reset

      184
    • 7.7.5 C64x+ Local Reset (DSP Local Reset)

      185
    • 7.7.6 Peripheral Local Reset

      185
    • 7.7.7 Reset Priority

      185
      • 7.7.7.1 Reset Type Status (RSTYPE) Register

        186
    • 7.7.8 Pin Behaviors at Reset

      186
    • 7.7.9 Reset Electrical Data/Timing

      190
  • 7.8 Interrupts

    193
    • 7.8.1 ARM CPU Interrupts

      193
    • 7.8.2 DSP Interrupts

      196
  • 7.9 External Memory Interface (EMIF)

    199
    • 7.9.1 Asynchronous EMIF (EMIFA)

      199
    • 7.9.2 NAND (NAND, SmartMedia/SSFDC, xD)

      199
    • 7.9.3 EMIFA Peripheral Register Description(s)

      199
    • 7.9.4  EMIFA Electrical Data/Timing

      201
  • 7.10 DDR2 Memory Controller

    206
    • 7.10.1 DDR2 Memory Controller Electrical Data/Timing

      207
    • 7.10.2 DDR2 Interface

      207
      • 7.10.2.1 DDR2 Interface Schematic

        207
      • 7.10.2.2 Compatible JEDEC DDR2 Devices

        207
      • 7.10.2.3 PCB Stackup

        208
      • 7.10.2.4 Placement

        211
      • 7.10.2.5 DDR2 Keep Out Region

        212
      • 7.10.2.6 Bulk Bypass Capacitors

        213
      • 7.10.2.7 High-Speed Bypass Capacitors

        213
      • 7.10.2.8 Net Classes

        213
      • 7.10.2.9 DDR2 Signal Termination

        214
      • 7.10.2.10 VREF Routing

        215
      • 7.10.2.11 DDR2 CK and ADDR_CTRL Routing

        215
  • 7.11 Video Port Interface (VPIF)

    219
    • 7.11.1 VPIF Bus Master Memory Map

      219
    • 7.11.2 VPIF Clock Control (Capture and Display)

      219
    • 7.11.3 VPIF Register Descriptions

      222
    • 7.11.4 VPIF Electrical Data/Timing

      225
  • 7.12 Transport Stream Interface (TSIF)

    227
    • 7.12.1 TSIF Bus Master

      227
    • 7.12.2 TSIF Clock Control

      228
    • 7.12.3 TSIF Peripheral Register Description(s)

      230
    • 7.12.4 Transport Stream Interface (TSIF) Electrical Data/Timing

      235
  • 7.13 Clock Recovery Generator (CRGEN)

    237
    • 7.13.1 CRGEN Peripheral Register Description(s)

      237
    • 7.13.2 CRGEN Electrical Data/Timing

      239
  • 7.14 Video Data Conversion Engine (VDCE)

    240
    • 7.14.1 VDCE Bus Master

      240
    • 7.14.2 VDCE Register Description(s)

      241
  • 7.15 Peripheral Component Interconnect (PCI)

    243
    • 7.15.1 PCI Device-Specific Information

      243
    • 7.15.2 PCI External Master Memory Map

      244
    • 7.15.3 PCI Peripheral Register Description(s)

      245
    • 7.15.4 PCI Electrical Data/Timing

      248
  • 7.16 Ethernet MAC (EMAC)

    249
    • 7.16.1 EMAC Device-Specific Information

      249
    • 7.16.2 EMAC Bus Master Memory Map

      250
    • 7.16.3 EMAC Peripheral Register Description(s)

      251
    • 7.16.4 EMAC Electrical Data/Timing

      255
  • 7.17  Management Data Input/Output (MDIO)

    259
    • 7.17.1  MDIO Peripheral Register Description(s)

      259
    • 7.17.2  Management Data Input/Output (MDIO) Electrical Data/Timing

      260
  • 7.18 Host-Port Interface (HPI) Peripheral

    261
    • 7.18.1 HPI Device-Specific Information

      261
    • 7.18.2 HPI Bus Master

      261
    • 7.18.3 HPI Peripheral Register Description(s)

      262
    • 7.18.4 HPI Electrical Data/Timing

      263
  • 7.19 USB 2.0 [see Note]

    269
    • 7.19.1 USB DMA Master

      269
    • 7.19.2 USB2.0 Device-Specific Information

      270
    • 7.19.3 USB2.0 Peripheral Register Description(s)

      271
    • 7.19.4 USB2.0 Electrical Data/Timing

      278
  • 7.20  ATA Controller

    279
    • 7.20.1 ATA Bus Master Memory Map

      279
    • 7.20.2 ATA Peripheral Register Description(s)

      280
    • 7.20.3 ATA Electrical Data/Timing

      281
      • 7.20.3.1 ATA PIO Data Transfer AC Timing

        281
      • 7.20.3.2 ATA Multiword DMA Timing

        283
      • 7.20.3.3 ATA Ultra DMA Timing

        285
      • 7.20.3.4 ATA HDDIR Timing

        292
  • 7.21 VLYNQ

    294
    • 7.21.1 VLYNQ Bus Master Memory Map

      294
    • 7.21.2 VLYNQ Peripheral Register Description(s)

      295
    • 7.21.3 VLYNQ Electrical Data/Timing

      297
  • 7.22  Multichannel Audio Serial Port (McASP0/1) Peripherals

    299
    • 7.22.1  McASP Device-Specific Information

      299
    • 7.22.2  McASP0 and McASP1 Peripheral Register Description(s)

      300
    • 7.22.3  McASP0 and McASP1 Electrical Data/Timing

      305
      • 7.22.3.1  Multichannel Audio Serial Port (McASP0) Timing

        305
      • 7.22.3.2  Multichannel Audio Serial Port (McASP1) DIT Timing

        309
  • 7.23 Serial Peripheral Interface (SPI)

    311
    • 7.23.1 SPI Device-Specific Information

      311
    • 7.23.2 SPI Peripheral Register Description(s)

      311
    • 7.23.3 SPI Electrical Data/Timing

      312
  • 7.24 Universal Asynchronouse Receiver/Transmitter (UART)

    326
    • 7.24.1 UART Device-Specific Information

      326
    • 7.24.2 UART Peripheral Register Description(s)

      327
    • 7.24.3 UART Electrical Data/Timing [Receive/Transmit]

      331
    • 7.24.4 IrDA Interface Receive/Transmit Timings

      332
  • 7.25 Inter-Integrated Circuit (I2C)

    333
    • 7.25.1  I2C Peripheral Register Description(s)

      334
    • 7.25.2  I2C Electrical Data/Timing

      335
  • 7.26 Pulse Width Modulator (PWM)

    337
    • 7.26.1 PWM Device-Specific Information

      337
    • 7.26.2 PWM Peripheral Register Description(s)

      337
    • 7.26.3 PWM0/1 Electrical Data/Timing

      338
  • 7.27 Timers

    339
    • 7.27.1 Timers Device-Specific Information

      339
    • 7.27.2  Timer Peripheral Register Description(s)

      339
    • 7.27.3  Timer Electrical Data/Timing

      341
  • 7.28 General-Purpose Input/Output (GPIO)

    342
    • 7.28.1 GPIO Device-Specific Information

      342
    • 7.28.2  GPIO Peripheral Register Description(s)

      343
    • 7.28.3  GPIO Peripheral Input/Output Electrical Data/Timing

      344
  • 7.29 IEEE 1149.1 JTAG

    345
    • 7.29.1  JTAG ID (JTAGID) Register Description(s)

      345
    • 7.29.2  JTAG Test-Port Electrical Data/Timing

      346
• 8 Mechanical Packaging and Orderable Information

  348
  • 8.1 Thermal Data for CUT

    348
  • 8.2 Packaging Information

    348