Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
3.3.8.3
DSP Memories
The ARM has access to the following DSP memories:
•
L2 RAM
•
L1P RAM
•
L1D RAM
3.3.8.4
ARM-DSP Integration
DM6467T ARM and DSP integration features are as follows:
•
DSP visibility from ARM’s memory map, see
, Memory Map Summary, for details
•
Boot Modes for DSP - see Device Configurations section,
, DSP Boot, for details
•
ARM control of DSP boot / reset - see Device Configurations section,
, ARM Boot, for
details
•
ARM control of DSP isolation and powerdown / powerup - see
, Device Configurations, for
details
•
ARM & DSP Interrupts - see
, ARM CPU Interrupts, and
, DSP Interrupts, for
details
3.3.9
Peripherals
The ARM9 has access to all of the peripherals on the DM6467T device.
3.3.10 PLL Controller (PLLC)
The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for
configuring DM6467T’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following
configuration and control:
configuring DM6467T’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following
configuration and control:
•
PLL Bypass Mode
•
Set PLL multiplier parameters
•
Set PLL divider parameters
•
PLL power down
•
Oscillator power down
The PLLs are briefly described in this document in the Clocking section. For more detailed information on
the PLLs and PLL Controller register descriptions, see the TMS320DM646x DMSoC ARM Subsystem
Reference Guide (literature number
the PLLs and PLL Controller register descriptions, see the TMS320DM646x DMSoC ARM Subsystem
Reference Guide (literature number
).
3.3.11 Power and Sleep Controller (PSC)
The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings
accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating
and power domain shut-off. Brief details on the PSC are given in
accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating
and power domain shut-off. Brief details on the PSC are given in
, Power Supplies. For more
detailed information and complete register descriptions for the PSC, see the TMS320DM646x DMSoC
ARM Subsystem Reference Guide (literature number
ARM Subsystem Reference Guide (literature number
).
3.3.12 ARM Interrupt Controller (AINTC)
The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ
(interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this
document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see the
TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
(interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this
document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see the
TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
Copyright © 2009–2012, Texas Instruments Incorporated
Device Overview
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