Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
4.7.3.12 Emulation Control
The flexibility of the DM646xT DMSoC architecture allows either the ARM or DSP to control the various
peripherals (setup registers, service interrupts, etc.). While this assignment is purely a matter of software
convention, during an emulation halt it is necessary for the device to know which peripherals are
associated with the halting processor so that only those modules receive the suspend signal. This allows
peripherals associated with the other (unhalted) processor to continue normal operation. The SUSPSRC
register indicates the emulation suspend source for those peripherals which support emulation suspend.
peripherals (setup registers, service interrupts, etc.). While this assignment is purely a matter of software
convention, during an emulation halt it is necessary for the device to know which peripherals are
associated with the halting processor so that only those modules receive the suspend signal. This allows
peripherals associated with the other (unhalted) processor to continue normal operation. The SUSPSRC
register indicates the emulation suspend source for those peripherals which support emulation suspend.
The SUSPSRC register format is shown in
. Brief details on the peripherals which correspond
to the register bits are listed in
. When the associated SUSPSRC bit is ‘0’, the peripheral’s
emulation suspend signal is controlled by the ARM emulator and when set to ‘1’ it is controlled by the DSP
emulator.
emulator.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CRGEN1
CRGEN0
TIMR2
TIMR1
TIMR0
GPIO
PWM1
PWM0
SPI
UART2
UART1
UART0
I2C
MCASP1
MCASP0
RSV
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
SRC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
13
12
11
10
9
8
7
6
5
4
3
0
HPI
EMAC
USB
VDCE
TSIF1
TSIF0
VPIF
RESERVED
RSV
RSV
RESERVED
SRC
SRC
SRC
SRC
SRC
SRC
SRC
R-000
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
R-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-26. SUSPSRC Register
Table 4-45. SUSPSRC Register Bit Descriptions
BIT
NAME
DESCRIPTION
Clock Recovery Generator 1 Emulation Suspend Source.
31
CRGEN1SRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
Clock Recovery Generator 0 Emulation Suspend Source.
30
CRGEN0SRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
Timer2 (WD Timer) Emulation Suspend Source.
29
TIMR2SRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
Timer1 Emulation Suspend Source.
28
TIMR1SRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
Timer0 Emulation Suspend Source.
27
TIMR0SRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
GPIO Emulation Suspend Source.
26
GPIOSRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
25
RSV
Reserved. Read returns "0".
PWM1 Emulation Suspend Source.
24
PWM1SRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
PWM0 Emulation Suspend Source.
23
PWM0SRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
SPI Emulation Suspend Source.
22
SPISRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
UART2 Emulation Suspend Source.
21
UART2SRC
0 = ARM emulation suspend.
1 = DSP emulation suspend.
1 = DSP emulation suspend.
130
Device Configurations
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