Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
6.2
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply voltage, Core (CV
DD
, DEV_CV
DD
,
CV
DD
(-1G)
1.235
1.3
1.365
V
AUX_CV
DD
)
(1)
Supply voltage, I/O, 3.3V (DV
DD33
, USB_V
DDA3P3
)
3.14
3.3
3.46
V
DV
DD
Supply voltage, I/O, 1.8V (DV
DDR2
, PLL1V
DD18
, PLL2V
DD18
,
1.71
1.8
1.89
V
DEV_DV
DD18
, AUX_DV
DD18
, USB_V
DD1P8
(2)
)
Supply ground (V
SS
, PLL1V
SS
, PLL2V
SS
, DEV_V
SS
(3)
,
V
SS
0
0
0
V
AUX_V
SS
(3)
, USB_V
SSREF
)
DDR_VREF
DDR2 reference voltage
(4)
0.49DV
DDR2
0.5DV
DDR2
0.51DV
DDR2
V
DDR2 impedance control, connected via 50-
Ω
(±5%
DDR_ZP
V
SS
V
tolerance) resistor to V
SS
DDR2 impedance control, connected via 50-
Ω
(±5%
DDR_ZN
DV
DDR2
V
tolerance) resistor to DV
DDR2
High-level input voltage, 3.3 V (except JTAG[TCK], PCI-
2
V
capable, and I2C pins)
High-level input voltage, JTAG [TCK]
2.5
V
V
IH
High-level input voltage, PCI
0.5DV
DD33
V
High-level input voltage, I2C
0.7DV
DD33
V
High-level input voltage, non-DDR I/O, 1.8 V
0.65DV
DD18
V
Low-level input voltage, 3.3 V (except PCI-capable and I2C
0.8
V
pins)
Low-level input voltage, PCI
0.3DV
DD33
V
V
IL
Low-level input voltage, I2C
0
0.3DV
DD33
V
Low-level input voltage, non-DDR I/O, 1.8 V
0.35DV
DD18
V
Default
0
85
°C
T
c
Operating case temperature
D Version
-40
85
°C
F
SYSCLK1
DSP Operating Frequency (SYSCLK1)
-1G
20
1
GHz
(1)
Future variants of TI SoC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2 V, 1.26 V, 1.3 V, 1.365 V with ± 3% tolerances) by implementing simple board changes such as reference resistor
values or input pin configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future
versions of TI SoC devices.
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2 V, 1.26 V, 1.3 V, 1.365 V with ± 3% tolerances) by implementing simple board changes such as reference resistor
values or input pin configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future
versions of TI SoC devices.
(2)
Oscillator 1.8 V power supply (DEV_DV
DD18
) can be connected to the same 1.8 V power supply as DV
DDR2
.
(3)
Oscillator ground (DEV_V
SS
and AUX_V
SS
) must be kept separate from other grounds and connected directly to the crystal load
capacitor ground.
(4)
DDR_VREF is expected to equal 0.5DV
DDR2
of the transmitting device and to track variations in the DV
DDR2
.
136
Device Operating Conditions
Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s):