Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.1.3
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
For the DDR2 memory controller interface, it is not necessary to use the IBIS models to analyze timing
characteristics.
characteristics.
, DDR2 Interface, provides a PCB routing rules solution that describes the
routing rules to ensure the DDR2 memory controller interface timings are met.
7.2
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic
manner.
140
Peripheral Information and Electrical Specifications
Copyright © 2009–2012, Texas Instruments Incorporated
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