Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 7-7. PLL1 and PLL2 Multiplier Ranges
-1G
PLL MULTIPLIER (PLLM)
MIN
MAX
PLL1 Multiplier
x14
x32
PLL2 Multiplier
x14
x32
Table 7-8. PLLC1 Clock Frequency Ranges
-1G
CLOCK SIGNAL NAME
UNIT
MIN
MAX
DEV_MXI/DEV_CLKIN
(1)
20
35
MHz
PLLOUT
400
1000
MHz
SYSCLK1 (PLLDIV1 Domain)
1000
MHz
(1)
DEV_MXI/DEV_CLKIN input clock is used for both PLL Controllers
(PLLC1 and PLLC2).
(PLLC1 and PLLC2).
Table 7-9. PLLC2 Clock Frequency Ranges
-1G
CLOCK SIGNAL NAME
UNIT
MIN
MAX
DEV_MXI/DEV_CLKIN
(1)
20
35
MHz
PLLOUT
400
800
MHz
PLL2_SYSCLK1 (to DDR2 PHY)
800
MHz
(1)
DEV_MXI/DEV_CLKIN input clock is used for both PLL Controllers
(PLLC1 and PLLC2).
(PLLC1 and PLLC2).
Both PLL1 and PLL2 have stabilization, lock, and reset timing requirements that must be followed.
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after the PLL is powered up (after the PLLCTL.PLLPWRDN bit goes through a 1-to-0
transition). The PLL should not be operated until this stabilization time has expired. This stabilization step
must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the
PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see
become stable after the PLL is powered up (after the PLLCTL.PLLPWRDN bit goes through a 1-to-0
transition). The PLL should not be operated until this stabilization time has expired. This stabilization step
must be applied after these resets—a Power-on Reset, a Warm Reset, or a Max Reset, as the
PLLCTL.PLLPWRDN bit resets to a "1". For the PLL stabliziation time value, see
The PLL reset time is the amount of wait time needed for the PLL to properly reset (writing PLLRST = 1)
before bringing the PLL out of reset (writing PLLRST = 0). For the PLL reset time value, see
before bringing the PLL out of reset (writing PLLRST = 0). For the PLL reset time value, see
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 0
with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the
PLL lock time value, see
with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the
PLL lock time value, see
.
Table 7-10. PLL1 and PLL2 Stabilization, Lock, and Reset Times
PLL STABILIZATION/
MIN
NOM
MAX
UNIT
LOCK/RESET TIME
PLL Stabilization Time
150
μ
s
PLL Lock Time
2000C
(1)
ns
PLL Reset Time
128C
(1)
ns
(1)
C = CLKIN cycle time in ns. For example, when DEV_MXI/DEV_CLKIN or AUX_MXI/AUX_CLKIN
frequency is 27 MHz, use C = 37.037 ns.
frequency is 27 MHz, use C = 37.037 ns.
154
Peripheral Information and Electrical Specifications
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