Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.20
ATA Controller
The ATA peripheral supports the following features:
•
PIO, multiword DMA, and Ultra ATA 33/66/100
•
Up to mode 4 timings on PIO mode
•
Up to mode 2 timings on multiword DMA
•
Up to mode 5 timings on Ultra ATA
•
Programmable timing parameters
•
Supports TrueIDE mode for Compact Flash
7.20.1 ATA Bus Master Memory Map
The ATA Controller supports multiword DMA transfers between external IDE/ATAPI devices and a system
memory bus interface.
memory bus interface.
shows the memory map for the ATA DMA engine.
Table 7-88. ATA DMA Master Memory Map
SIZE
START ADDRESS
END ADDRESS
ATA DMA ACCESS
(BYTES)
0x0000 0000
0x0FFF FFFF
256M
Reserved
0x1000 0000
0x1000 FFFF
64K
Reserved
0x1001 0000
0x1001 3FFF
16K
ARM RAM 0 (Data)
0x1001 4000
0x1001 7FFF
16K
ARM RAM 1 (Data)
0x1001 8000
0x1001 FFFF
32K
ARM ROM (Data)
0x1002 0000
0x10FF FFFF
16256K
0x1100 0000
0x113F FFFF
4M
0x1140 0000
0x114F FFFF
1M
0x1150 0000
0x115F FFFF
1M
Reserved
0x1160 0000
0x116F FFFF
1M
0x1170 0000
0x117F FFFF
1M
0x1180 0000
0x1180 FFFF
64K
0x1181 0000
0x1181 7FFF
32K
0x1181 8000
0x1183 7FFF
128K
C64x+ L2 RAM/Cache
0x1183 8000
0x118F FFFF
800K
Reserved
0x1190 0000
0x11DF FFFF
5M
0x11E0 0000
0x11E0 7FFF
32K
C64x+ L1P RAM/Cache
0x11E0 8000
0x11EF FFFF
992K
Reserved
0x11F0 0000
0x11F0 7FFF
32K
C64x+ L1D RAM/Cache
0x11F0 8000
0x11FF FFFF
992K
Reserved
0x1200 0000
0x4BFF FFFF
928M
0x4C00 0000
0x4FFF FFFF
64M
VLYNQ (Remote Data)
0x5000 0000
0x7FFF FFFF
768M
Reserved
0x8000 0000
0x9FFF FFFF
512M
DDR2 Memory Controller
0xA000 0000
0xBFFF FFFF
512M
Reserved
0xC000 0000
0xFFFF FFFF
1G
Reserved
Copyright © 2009–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
279
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