Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
25
23
19
18
22
27
20
21
17
18
28
Stop
Start
Repeated
Start
Stop
SDA
SCL
16
26
24
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 7-135. Switching Characteristics for I2C Timings
(1)
(see
-1G
STANDARD
NO.
PARAMETER
FAST MODE
UNIT
MODE
MIN
MAX
MIN
MAX
16
t
c(SCL)
Cycle time, SCL
10
2.5
µs
Delay time, SCL high to SDA low (for a repeated START
17
t
d(SCLH-SDAL)
4.7
0.6
µs
condition)
Delay time, SDA low to SCL low (for a START and a repeated
18
t
d(SDAL-SCLL)
4
0.6
µs
START condition)
19
t
w(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
20
t
w(SCLH)
Pulse duration, SCL high
4
0.6
µs
21
t
d(SDAV-SCLH)
Delay time, SDA valid to SCL high
250
100
ns
22
t
v(SCLL-SDAV)
Valid time, SDA valid after SCL low
0
0
0.9
µs
Pulse duration, SDA high between STOP and START
23
t
w(SDAH)
4.7
1.3
µs
conditions
20 + 0.1C
b
24
t
r(SDA)
Rise time, SDA
1000
300
ns
(2)
20 + 0.1C
b
25
t
r(SCL)
Rise time, SCL
1000
300
ns
(2)
20 + 0.1C
b
26
t
f(SDA)
Fall time, SDA
300
300
ns
(2)
20 + 0.1C
b
27
t
f(SCL)
Fall time, SCL
300
300
ns
(2)
28
t
d(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
4
0.6
µs
29
C
p
Capacitance for each I2C pin
10
10
pF
(1)
C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2)
C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 7-90. I2C Transmit Timings
336
Peripheral Information and Electrical Specifications
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