Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T Datenbogen
Produktcode
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
4.3.2.2
TSIF Control
The TSIF Control (TSIFCTL) registers allows the user to select/control the clock muxing for the counter
and serial output of TSIF1 andthe counter and parallel/serial output for TSIF0.
and serial output of TSIF1 andthe counter and parallel/serial output for TSIF0.
31
16
RESERVED
R-0000 0000 0000 0000
15
14
12
11
8
7
6
4
3
2
0
RSV
TSIF1_CNTCLK
TSSO_CLK
RSV
TSIF0_CNTCLK
RSV
TSPO_CLK
R-0
R/W-000
R/W-0000
R-0
R/W-000
R-0
R/W-000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-3. TSIFCTL Register [0x01C4 0050]
Table 4-5. TSIFCTL Register Bit Descriptions
BIT
NAME
DESCRIPTION
31:15
RESERVED
Reserved. Read returns "0".
TSIF1 Counter Clock Source.
This field selects the clock source for the TSIF1 module's counter.
000 = CRG1_VCXI (external pin)
001 = STC_CLKIN (external pin)
010 = AUXCLK (PLLC1 output)
This field selects the clock source for the TSIF1 module's counter.
000 = CRG1_VCXI (external pin)
001 = STC_CLKIN (external pin)
010 = AUXCLK (PLLC1 output)
14:12
TSIF1_CNTCLK
011 = CRG0_VCXI (external pin)
100 = VP_CLKIN2 (external pin)
101 = VP_CLKIN3 (external pin)
110 = Reserved
111 = Reserved
100 = VP_CLKIN2 (external pin)
101 = VP_CLKIN3 (external pin)
110 = Reserved
111 = Reserved
TSIF1 Serial Output Clock Source.
This field selects the clock source for the TSIF1 output source clock.
0000 = CRG1_VCXI (external pin)
0001 = STC_CLKIN (external pin)
0010 = SYSCLK6 (PLLC1)
0011 = SYSCLKBP (PLLC1)
This field selects the clock source for the TSIF1 output source clock.
0000 = CRG1_VCXI (external pin)
0001 = STC_CLKIN (external pin)
0010 = SYSCLK6 (PLLC1)
0011 = SYSCLKBP (PLLC1)
11:8
TSSO_CLK
0100 = VP_CLKIN0 (external pin)
0101 = TS1_CLKIN (external pin)
0110 = VP_CLKIN2 (external pin)
0111 = Reserved
1000 = CRG0_VCXI
1001 = Reserved
1xx1 = Reserved
0101 = TS1_CLKIN (external pin)
0110 = VP_CLKIN2 (external pin)
0111 = Reserved
1000 = CRG0_VCXI
1001 = Reserved
1xx1 = Reserved
7
RSV
Reserved. Read returns "0".
TSIF0 Counter Clock Source.
This field selects the clock source for the TSIF0 module's counter.
000 = CRG0_VCXI (external pin)
001 = STC_CLKIN (external pin)
010 = AUXCLK (PLLC1 output)
This field selects the clock source for the TSIF0 module's counter.
000 = CRG0_VCXI (external pin)
001 = STC_CLKIN (external pin)
010 = AUXCLK (PLLC1 output)
6:4
TSIF0_CNTCLK
011 = CRG1_VCXI (external pin)
100 = VP_CLKIN0 (external pin)
101 = VP_CLKIN1 (external pin)
110 = Reserved
111 = Reserved
100 = VP_CLKIN0 (external pin)
101 = VP_CLKIN1 (external pin)
110 = Reserved
111 = Reserved
3
RSV
Reserved. Read returns "0".
TSIF0 Parallel/Serial Output Clock Source.
This field selects the clock source for the TSIF0 output source clock.
000 = CRG0_VCXI (external pin)
001 = STC_CLKIN (external pin)
010 = SYSCLK5 (PLLC1)
This field selects the clock source for the TSIF0 output source clock.
000 = CRG0_VCXI (external pin)
001 = STC_CLKIN (external pin)
010 = SYSCLK5 (PLLC1)
2:0
TSPO_CLK
011 = SYSCLKBP (PLLC1)
100 = VP_CLKIN0 (external pin)
101 = VP_CLKIN1 (external pin)
110 = TS0_CLKIN (external pin)
111 = CRG1_VCXI (external pin)
100 = VP_CLKIN0 (external pin)
101 = VP_CLKIN1 (external pin)
110 = TS0_CLKIN (external pin)
111 = CRG1_VCXI (external pin)
Copyright © 2009–2012, Texas Instruments Incorporated
Device Configurations
89
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